公开(公告)号：US06566148B2

公开(公告)日：2003-05-20

申请号：US09929710

申请日：2001-08-13

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Bruce D. Ulrich

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Bruce D. Ulrich

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684

摘要： A method of making a ferroelectric memory transistor includes preparing a silicon substrate including forming plural active areas thereon; depositing a layer of gate insulator on the substrate, and depositing a layer of polysilicon over the gate insulator layer; forming a source region, a drain region and a gate electrode; depositing a layer of bottom electrode material and finishing the bottom electrode without damaging the underlying gate insulator and silicon substrate; depositing a layer of ferroelectric material on the bottom electrode; depositing a layer of top electrode material on the ferroelectric material; and finishing the transistor, including passivation oxide deposition, contact hole etching and metalization.

摘要翻译： 制造铁电存储晶体管的方法包括制备包括在其上形成多个有源区的硅衬底; 在所述衬底上沉积栅极绝缘体层，以及在所述栅极绝缘体层上沉积多晶硅层; 形成源极区域，漏极区域和栅极电极; 沉积一层底部电极材料并整理底部电极，而不损坏下面的栅极绝缘体和硅衬底; 在底部电极上沉​​积一层铁电材料; 在铁电材料上沉积顶层电极材料层; 并整理晶体管，包括钝化氧化物沉积，接触孔蚀刻和金属化。

公开(公告)号：US06531324B2

公开(公告)日：2003-03-11

申请号：US09820039

申请日：2001-03-28

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L2100

CPC分类号： H01L29/516 ,  H01L21/28291 ,  H01L29/78391

摘要： A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

公开(公告)号：US06495378B2

公开(公告)日：2002-12-17

申请号：US09814273

申请日：2001-03-21

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/02197 ,  C23C16/40 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31691

摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

摘要翻译： 提供Pb3GeO5相PGO薄膜。 该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。 该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。 该方法将Pd和锗在溶剂中混合。 将溶液加热以形成分解的前体蒸汽。 该方法提供沉积温度和压力。 沉积的膜也被退火以增强膜的铁弹性特征。 还提供了由本发明PGO膜制成的铁弹性电容器。

公开(公告)号：US06190925B1

公开(公告)日：2001-02-20

申请号：US09302272

申请日：1999-04-28

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L21/31691 ,  Y10S438/933

摘要： The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb5Ge3O11 thin films along with c-axis orientation.

摘要翻译： 本发明提供了具有最佳铁电性能的基本单晶PGO膜。 PGO膜和相邻电极被外延生长以最小化结构之间的失配。 MOCVD沉积方法和RTP退火程序允许PGO膜在商业制造工艺中外延生长。 这些外延铁电体已经应用于FeRAM存储器件中。 本发明沉积方法外延生长铁电Pb5Ge3O11薄膜以及c轴取向。

公开(公告)号：US07598108B2

公开(公告)日：2009-10-06

申请号：US11825427

申请日：2007-07-06

申请人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L29/155 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02647 ,  H01L29/2003 ,  H01L29/205

摘要： A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al1-XGaXN layer is formed overlying the third layer of AlN, where 0

公开(公告)号：US20090008647A1

公开(公告)日：2009-01-08

申请号：US11825427

申请日：2007-07-06

申请人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L29/15 ,  H01L21/20

CPC分类号： H01L29/155 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02647 ,  H01L29/2003 ,  H01L29/205

摘要： A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al1-XGaXN layer is formed overlying the third layer of AlN, where 0

摘要翻译： 已经提供了使用多种铝化合物缓冲层的硅（Si）和氮化镓（GaN）膜之间的热膨胀界面，以及相关的制造方法。 该方法提供（111）Si衬底，并通过将衬底加热至1000至1200℃的较高温度，将衬底上的第一层AlN沉积在衬底上。在第一层AlN上沉积第二层AlN， 较低温度为500至800℃。通过将衬底加热到​​较高温度范围，沉积第三层AlN，覆盖第二层AlN。 然后，形成覆盖在第一层次Al1-XGaXN层上的固定组成Al1-XGaXN层的覆盖在第三层AlN上的分级Al1-XGaXN层，其中0

公开(公告)号：US20080296625A1

公开(公告)日：2008-12-04

申请号：US11810022

申请日：2007-06-04

申请人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647

摘要： A multilayer thermal expansion interface between silicon (Si) and gallium nitride (GaN) films is provided, along with an associated fabrication method. The method provides a (111) Si substrate and forms a first layer of a first film overlying the substrate. The Si substrate is heated to a temperature in the range of about 300 to 800° C., and the first layer of a second film is formed in compression overlying the first layer of the first film. Using a lateral nanoheteroepitaxy overgrowth (LNEO) process, a first GaN layer is grown overlying the first layer of second film. Then, the above-mentioned processes are repeated: forming a second layer of first film; heating the substrate to a temperature in the range of about 300 to 800° C.; forming a second layer of second film in compression; and, growing a second GaN layer using the LNEO process.

摘要翻译： 提供硅（Si）和氮化镓（GaN）膜之间的多层热膨胀界面以及相关的制造方法。 该方法提供（111）Si衬底并且形成覆盖衬底的第一膜的第一层。 将Si衬底加热至约300至800℃的温度，并且第二膜的第一层以压缩形式覆盖第一膜的第一层。 使用横向纳米外延过度生长（LNEO）工艺，生长第一GaN层，覆盖第一层第二层膜。 然后，重复上述过程：形成第二层第一膜; 将基板加热至约300至800℃的温度; 在压缩中形成第二层第二膜; 并且使用LNEO工艺生长第二GaN层。

公开(公告)号：US20080296616A1

公开(公告)日：2008-12-04

申请号：US11809958

申请日：2007-06-04

申请人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/20 ,  H01L29/20

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647

摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate that is heated to a temperature in a range of about 300 to 800° C., and a first film is formed in compression overlying the Si substrate. The first film material may be InP, SiGe, GaP, GaAs, AlN, AlGaN, an AlN/graded AlGaN (Al1−xGaxN (0

摘要翻译： 提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。 该方法提供加热至约300至800℃范围内的温度的（111）Si衬底，并且第一膜以压缩形式覆盖Si衬底。 第一膜材料可以是InP，SiGe，GaP，GaAs，AlN，AlGaN，AlN /分级AlGaN（Al1-xGaxN（0

公开(公告)号：US20080166878A1

公开(公告)日：2008-07-10

申请号：US11651242

申请日：2007-01-08

申请人： Tingkai Li ,  Bruce D. Ulrich ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Bruce D. Ulrich ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/306

CPC分类号： H01L21/31111 ,  B81C1/00111 ,  H01L21/3065 ,  H01L21/31122

摘要： A method of fabricating silicon nanostructures includes preparing a silicon wafer as a substrate; forming an oxide layer hardmask directly on the silicon substrate; patterning and etching the oxide hardmask; wet etching the silicon wafer to remove oxide to reduce the size of the oxide hardmask and to form nanostructure elements; and dry etching, in one or more steps, the silicon wafer using the oxide hardmask to form a desired nanostructure having substantially parallel vertical sidewalls thereon.

摘要翻译： 制造硅纳米结构的方法包括制备硅晶片作为基底; 在硅衬底上直接形成氧化层硬掩模; 图案化和蚀刻氧化物硬掩模; 湿蚀刻硅晶片以除去氧化物以减小氧化物硬掩模的尺寸并形成纳米结构元件; 以及使用氧化物硬掩模在一个或多个步骤中干蚀刻硅晶片以形成其上具有基本上平行的垂直侧壁的所需纳米结构。

公开(公告)号：US20080164577A1

公开(公告)日：2008-07-10

申请号：US11649634

申请日：2007-01-04

申请人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/3065 ,  H01L29/06

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/306 ,  H01L29/0669 ,  H01L29/0673 ,  Y10S977/743

摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.

摘要翻译： 亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。 该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。 由二氧化硅膜形成二氧化硅棒的阵列，并且在二氧化硅棒周围形成Si 3 N 4 N 4管。 二氧化硅棒被蚀刻掉。 然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4 N 4管子下面的Si管。 最后，去除Si 3 N 4 N 4管。