公开(公告)号：US20080128834A1

公开(公告)日：2008-06-05

申请号：US12014931

申请日：2008-01-16

申请人： Haining Yang ,  Xiangdong Chen ,  Yong Meng Lee ,  Wenhe Lin

发明人： Haining Yang ,  Xiangdong Chen ,  Yong Meng Lee ,  Wenhe Lin

IPC分类号： H01L29/94 ,  H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/1033 ,  H01L29/4933 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer over a transistor device, ion implanting a species into the silicon nitride layer to drive hydrogen from the silicon nitride layer, and annealing to diffuse the hydrogen into a channel region of the transistor device. The species may be chosen from, for example: germanium (Ge), arsenic (As), xenon (Xe), nitrogen (N), oxygen (O), carbon (C), boron (B), indium (In), argon (Ar), helium (He), and deuterium (De). The ion implantation modulates atoms in the silicon nitride layer such as hydrogen, nitrogen and hydrogen-nitrogen bonds such that hydrogen can be controllably diffused into the channel region.

摘要翻译： 公开了减少热载流子劣化的方法和如此形成的半导体结构。 该方法的一个实施例包括在晶体管器件上沉积氮化硅层，将物质离子注入到氮化硅层中以从氮化硅层驱动氢，以及退火以将氢扩散到晶体管器件的沟道区域。 该物质可以选自例如：锗（Ge），砷（As），氙（Xe），氮（N），氧（O），碳（C），硼（B），铟（In） 氩（Ar），氦（He）和氘（De）。 离子注入调节氮化硅层中的原子，例如氢，氮和氢 - 氮键，使得氢可以可控地扩散到沟道区中。

公开(公告)号：US20080121985A1

公开(公告)日：2008-05-29

申请号：US11557145

申请日：2006-11-07

申请人： Xiangdong Chen ,  Dae-Gyu Park ,  Jae-Yoon Yoo

发明人： Xiangdong Chen ,  Dae-Gyu Park ,  Jae-Yoon Yoo

IPC分类号： H01L27/088 ,  H01L21/04 ,  H01L29/78 ,  H01L21/77

CPC分类号： H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming these structures. The embodiments suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep source/drain regions and the channel region and, particularly, between deep source/drain regions and the halo regions. Buried isolation regions between the deep source/drain regions and the channel region minimize drain induced barrier lowering (DIBL) as well as punch through. Additionally, because the deep source/drain regions and halo regions are separated by the buried isolation regions, side-wall junction capacitance and junction leakage are also minimized.

摘要翻译： 公开了改进的MOSFET和CMOS结构的实施例，其提供对短沟道效应的增加的控制。 还公开了形成这些结构的相关方法的实施例。 这些实施例通过将掩埋隔离区域并入到源极/漏极延伸区域之下以及深源极/漏极区域和沟道区域之间，特别是在深源极/漏极区域和晕圈区域之间的晶体管中来抑制短沟道效应。 在深源极/漏极区域和沟道区域之间的埋置隔离区域最小化漏极引起的屏障降低（DIBL）以及穿通。 此外，由于深源极/漏极区域和晕圈区域被掩埋隔离区域分开，所以侧壁结电容和结漏电也被最小化。

公开(公告)号：US20080116524A1

公开(公告)日：2008-05-22

申请号：US12018851

申请日：2008-01-24

申请人： Xiangdong Chen ,  Haining Yang

发明人： Xiangdong Chen ,  Haining Yang

IPC分类号： H01L27/08

CPC分类号： H01L21/823807 ,  H01L29/7842

摘要： A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

摘要翻译： 提供一种半导体器件结构，其包括第一场效应晶体管（“FET”），其具有第一沟道区，第一源极区，第一漏极区和覆盖第一沟道区的第一栅极导体。 包括第二FET，其具有覆盖第二沟道区的第二沟道区，第二源极区，第二漏极区和第二栅极导体。 第一和第二栅极导体是在第一和第二沟道区两者上延伸的单个细长导电构件的部分。 第一应力膜覆盖第一FET，第一应力膜将具有第一值的应力施加到第一沟道区。 第二应力膜覆盖第二FET，第二应力膜向第二沟道区施加具有第二值的应力。 第二个值与第一个值大不相同。 此外，第一和第二应力膜在共同边界处彼此邻接并且在共同边界处呈现基本上共平面的主表面。

公开(公告)号：US07361539B2

公开(公告)日：2008-04-22

申请号：US11383560

申请日：2006-05-16

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L29/7842

摘要： A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

摘要翻译： 提供一种半导体器件结构，其包括第一场效应晶体管（“FET”），其具有第一沟道区，第一源极区，第一漏极区和覆盖第一沟道区的第一栅极导体。 包括第二FET，其具有覆盖第二沟道区的第二沟道区，第二源极区，第二漏极区和第二栅极导体。 第一和第二栅极导体是在第一和第二沟道区两者上延伸的单个细长导电构件的部分。 第一应力膜覆盖第一FET，第一应力膜将具有第一值的应力施加到第一沟道区。 第二应力膜覆盖第二FET，第二应力膜向第二沟道区施加具有第二值的应力。 第二个值与第一个值大不相同。 此外，第一和第二应力膜在共同边界处彼此邻接并且在共同边界处呈现基本上共平面的主表面。

公开(公告)号：US20080050881A1

公开(公告)日：2008-02-28

申请号：US11931341

申请日：2007-10-31

申请人： Xiangdong Chen ,  Haining Yang

发明人： Xiangdong Chen ,  Haining Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

摘要翻译： 本发明涉及异质结隧道效应晶体管（TFET），其包括间隔开的源极和漏极区，其中位于其间的沟道区和位于沟道区上方的栅极叠层。 漏极区域包括第一半导体材料并且掺杂有第一导电类型的第一掺杂物种类。 源区包括第二不同的半导体材料，并且掺杂有第二不同导电类型的第二掺杂物种。 栅极堆叠至少包括栅极电介质和栅极导体。 当异质结TFET是n沟道TFET时，漏极区域包括n掺杂的硅，而源极区域包括p掺杂的硅锗。 当异质结TFET是p沟道TFET时，漏极区包括p掺杂的硅，而源区包括n掺杂的碳化硅。

公开(公告)号：US20080001182A1

公开(公告)日：2008-01-03

申请号：US11427495

申请日：2006-06-29

申请人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

发明人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L27/148

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.

摘要翻译： 本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。 具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着 第二，不同组的等效晶面。 这种附加表面可以通过晶体蚀刻容易地形成。 此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。 这样的应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

公开(公告)号：US20070254420A1

公开(公告)日：2007-11-01

申请号：US11380743

申请日：2006-04-28

申请人： Atul Ajmera ,  Christopher Baiocco ,  Xiangdong Chen ,  Thomas Dyer ,  Sunfei Fang ,  Wenzhi Gao

发明人： Atul Ajmera ,  Christopher Baiocco ,  Xiangdong Chen ,  Thomas Dyer ,  Sunfei Fang ,  Wenzhi Gao

IPC分类号： H01L21/338 ,  H01L21/20 ,  H01L29/76

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： Methods for source/drain implantation and strain transfer to a channel of a semiconductor device and a related semiconductor device are disclosed. In one embodiment, the method includes using a first size spacer for deep source/drain implantation adjacent a gate region of a semiconductor device; and using a second, smaller size spacer for silicide formation adjacent the gate region and transferring strain from a stress liner to a channel underlying the gate region. One embodiment of a semiconductor device may include a gate region atop a substrate; a spacer including a spacer core and an outer spacer member about the spacer core; a deep source/drain region within the substrate and distanced from the spacer; and a silicide region within the substrate and overlapping and extending beyond the deep source/drain region, the silicide region aligned to the spacer.

摘要翻译： 公开了用于源极/漏极注入和应变转移到半导体器件和相关半导体器件的沟道的方法。 在一个实施例中，该方法包括使用与半导体器件的栅极区域相邻的深源极/漏极注入的第一尺寸间隔物; 并且使用第二较小尺寸的间隔物，用于邻近栅极区域的硅化物形成，并将应变从应力衬垫转移到栅极区域下方的沟道。 半导体器件的一个实施例可以包括位于衬底顶部的栅极区域; 间隔件，其包括间隔件芯和围绕所述间隔件芯的外部间隔件; 衬底内的深源极/漏极区域，并远离间隔物; 以及衬底内的硅化物区域，并且重叠并延伸超过深源极/漏极区域，硅化物区域与间隔物对准。

公开(公告)号：US20070051996A1

公开(公告)日：2007-03-08

申请号：US11553072

申请日：2006-10-26

申请人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

发明人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10864

摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

摘要翻译： 在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。 晶体管栅极被设计代替通道。 用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。 存储节点附近的栅极材料为n型掺杂多晶硅。 位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。 该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

公开(公告)号：US20070045611A1

公开(公告)日：2007-03-01

申请号：US11162126

申请日：2005-08-30

申请人： Huilong Zhu ,  Xiangdong Chen

发明人： Huilong Zhu ,  Xiangdong Chen

IPC分类号： H01L29/06

CPC分类号： H01L21/26506 ,  H01L21/28132 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78684 ,  H01L29/78696

摘要： The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.

摘要翻译： 本发明一般涉及具有包括第一半导体材料和第二不同材料的半导体合金的沟道区的半导体器件，并且其中沟道区中的第二材料的原子分布沿着基本平行的方向分级 到半导体器件所在的衬底表面。 具体地，半导体器件包括具有横向渐变的锗含量的SiGe沟道的场效应晶体管（FET）。

公开(公告)号：US20060258060A1

公开(公告)日：2006-11-16

申请号：US11487809

申请日：2006-07-17

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

IPC分类号： H01L21/339

CPC分类号： H01L27/10864 ,  H01L27/0214 ,  H01L27/10841

摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate over-drive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.

摘要翻译： 用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。 这使得晶体管在通常施加到存储和控制单元的两个门的有效字线电压期间表现出增加的栅极过驱动和驱动电流。