公开(公告)号：US07842618B2

公开(公告)日：2010-11-30

申请号：US11193409

申请日：2005-08-01

申请人： Unsoon Kim ,  Angela T. Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

发明人： Unsoon Kim ,  Angela T. Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11531

摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.

摘要翻译： 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。 沟槽填充有氧化物材料。 从存储器件剥离氮化物层，在沟槽上方形成台面。

公开(公告)号：US07834917B2

公开(公告)日：2010-11-16

申请号：US11665037

申请日：2006-08-09

申请人： Hiroyuki Kinoshita ,  Jing Zhang ,  Masahiro Ito ,  Akira Matsui

发明人： Hiroyuki Kinoshita ,  Jing Zhang ,  Masahiro Ito ,  Akira Matsui

IPC分类号： H04N5/217

CPC分类号： H04N5/21 ,  G06T3/4023 ,  G06T5/002 ,  G06T5/005 ,  G06T5/20 ,  G06T7/13 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20032 ,  G06T2207/20192 ,  H04N5/213

摘要： Noise reduction is performed on the basis of characteristics of an image in a detection range. A noise reduction block 4′ performs a second-order differentiation process and a symmetry process to decide adjacent pixels with which noise reduction is preformed for an attention pixel. With the pixel level of the attention pixel in the detection range and the pixel levels of adjacent pixels used for noise reduction, an arithmetic mean processing section 16 calculates a mean value. A median filter 17 selects a median value. With the number of pixels used for noise reduction, it is determined whether the image in the detection range contains a flat portion, a ramp portion, or an edge. The mean value and the median value are weight-added with a weighted coefficient that are changed on the basis of characteristics of the image. The result is substituted for the level of the attention pixel. When the attention pixel is an isolated point, an all-pixel median filter section 31 selects a medium value of the levels of all the pixels in the detection range including the attention pixel and substitutes the median value for the level of the attention pixel.

摘要翻译： 基于检测范围内的图像的特性进行降噪。 降噪块4'执行二阶微分处理和对称处理，以确定针对注意像素执行降噪的相邻像素。 利用检测范围内的关注像素的像素级和用于降噪的相邻像素的像素级，算术平均处理部16计算平均值。 中值滤波器17选择中值。 利用用于降噪的像素数量，确定检测范围内的图像是否包含平坦部分，斜坡部分或边缘。 平均值和中值是加权系数，加权系数根据图像的特性而改变。 结果代替注意像素的级别。 当注意像素是孤立点时，全像素中值滤波器部分31选择包括关注像素在内的检测范围内的所有像素的电平的中值，并代入关注像素的电平的中值。

公开(公告)号：US07679129B1

公开(公告)日：2010-03-16

申请号：US11128389

申请日：2005-05-13

申请人： Angela T. Hui ,  Unsoon Kim ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

发明人： Angela T. Hui ,  Unsoon Kim ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

IPC分类号： H01L29/94

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/66825

摘要： A memory device includes a substrate and a first dielectric layer formed over the substrate. At least two charge storage elements are formed over the first dielectric layer. The substrate and the first dielectric layer include a shallow trench filled with an oxide material. The oxide material formed in a center portion of the shallow trench is removed to provide a region with a substantially rectangular cross-section.

摘要翻译： 存储器件包括衬底和形成在衬底上的第一电介质层。 在第一电介质层上形成至少两个电荷存储元件。 衬底和第一介电层包括填充有氧化物材料的浅沟槽。 形成在浅沟槽的中心部分的氧化物材料被去除以提供具有基本上矩形横截面的区域。

公开(公告)号：US07666739B2

公开(公告)日：2010-02-23

申请号：US11614048

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/792

摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

摘要翻译： 提供了用于制造分离电荷存储节点半导体存储器件的方法。 根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极 。 栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。 第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构 厚度。

公开(公告)号：US20090108330A1

公开(公告)日：2009-04-30

申请号：US11924169

申请日：2007-10-25

申请人： Minghao Shen ,  Chungho Lee ,  Hiroyuki Kinoshita ,  Huaqiang Wu

发明人： Minghao Shen ,  Chungho Lee ,  Hiroyuki Kinoshita ,  Huaqiang Wu

IPC分类号： H01L29/792 ,  H01L21/3205

CPC分类号： H01L29/7923 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11568

摘要： Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

摘要翻译： 提供了包含半导体衬底上的两个分裂子光刻电荷存储节点的存储单元以及用于制造存储单元的方法。 这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。 通过在间隔物的倾斜侧表面或外表面之间除去第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。 此外，通过去除间隔物的倾斜侧表面或外表面之间的电荷存储层的暴露部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个分裂的亚光刻电荷存储节点。

公开(公告)号：US20090061631A1

公开(公告)日：2009-03-05

申请号：US11848515

申请日：2007-08-31

申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Rinji Sugino ,  Chi Chang ,  Huaqiang Wu

发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Rinji Sugino ,  Chi Chang ,  Huaqiang Wu

IPC分类号： H01L21/311

CPC分类号： H01L29/7923 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.

摘要翻译： 提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。 该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。 可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

公开(公告)号：US07432156B1

公开(公告)日：2008-10-07

申请号：US11409361

申请日：2006-04-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Meng Ding

IPC分类号： H01L21/8247

CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

摘要翻译： 提供半导体存储器件及其制造方法。 根据本发明的一个实施例，该方法包括以下步骤：形成栅极绝缘体和覆盖半导体衬底的栅电极。 蚀刻栅极绝缘体以在栅电极的边缘下方形成底切开口，并且底切开口填充有包括夹在氧化物层和氮化物层之间的电荷捕获层的分层结构。 掺杂半导体衬底的区域以形成与栅电极对准的位线，并且沉积并图案化导电层以形成耦合到栅电极的字线。

公开(公告)号：US20080153236A1

公开(公告)日：2008-06-26

申请号：US11615425

申请日：2006-12-22

申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Minh-Van Ngo ,  Fred Cheung ,  Alexander Nickel

发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Minh-Van Ngo ,  Fred Cheung ,  Alexander Nickel

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L27/115 ,  H01L27/11568

摘要： Flash memory devices and methods for fabricating the same are provided. A method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a P-type silicon substrate and implanting an impurity dopant into the substrate substantially between the first gate stack and the second gate stack to form an impurity-doped region of the substrate. A channel region underlies the first gate stack adjacent to the impurity-doped region. An intrinsically tensile-stressed insulating member is formed between the first and the second gate stacks and overlying the impurity-doped region. The tensile-stressed insulating member causes a uniaxial lateral tensile stress to be transmitted to the first channel region. A word line is formed overlying the intrinsically tensile-stressed insulating member and in electrical contact with the first gate stack and the second gate stack.

摘要翻译： 提供闪存器件及其制造方法。 一种用于制造存储器件的方法包括以下步骤：制造覆盖P型硅衬底的第一栅极堆叠和第二栅极堆叠，并且基本上在第一栅极堆叠和第二栅极堆叠之间将杂质掺杂剂注入到衬底中，以形成 衬底的杂质掺杂区域。 位于与杂质掺杂区相邻的第一栅叠层下方的沟道区。 在第一和第二栅极堆叠之间并且覆盖杂质掺杂区域上形成本征拉伸应力的绝缘构件。 拉伸应力绝缘构件使单向横向拉伸应力传递到第一沟道区域。 在本征拉伸应力绝缘构件上形成字线并且与第一栅极堆叠和第二栅极堆叠电接触。

公开(公告)号：US20080153228A1

公开(公告)日：2008-06-26

申请号：US11614050

申请日：2006-12-20

申请人： Ning Cheng ,  Hiroyuki Kinoshita ,  Minghao Shen ,  Ashot Melik-Martirosian

发明人： Ning Cheng ,  Hiroyuki Kinoshita ,  Minghao Shen ,  Ashot Melik-Martirosian

IPC分类号： H01L21/8239

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792

摘要： Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.

摘要翻译： 提供了用于制造包括双位存储单元的存储器件的方法。 该方法包括根据本发明的一个实施例，在半导体衬底的表面上形成覆盖栅极电介质层的栅极电介质层和中心栅电极。 第一和第二存储器存储节点形成在栅极电介质层的侧面附近，第一和第二存储节点中的每一个包括第一介电层和电荷存储层，第一电介质层独立于形成栅极电介质的步骤而形成 层。 第一控制栅极形成在第一存储器存储节点上，并且第二控制栅极形成在第二存储器存储节点上。 导电层被沉积并图案化以形成耦合到中央栅电极，第一控制栅极和第二控制栅极的字线。

公开(公告)号：US07301193B2

公开(公告)日：2007-11-27

申请号：US10762445

申请日：2004-01-22

申请人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/743 ,  H01L29/41766 ,  H01L29/66636

摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

摘要翻译： 根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。 浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。 根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。 浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。 位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。