Abstract:
A method and apparatus for signal gain adjustment within an RF integrated circuit (IC) include processing that begins by determining the signal strength of a received RF input signal with respect to a first signal strength scale to produce a signal strength indication. The processing continues by determining whether the signal strength indication exceeds a first high power threshold. If not, the receiver continues to process received RF signals without additional attenuation. If, however, the signal strength indication exceeds the first high power threshold, the received RF input signal is attenuated to produce an attenuated RF input signal. In addition, the first signal strength scale is shifted to produce a shifted signal strength scale. The processing continues by determining whether the signal strength of the attenuated RF input signal exceeds a high power threshold of the shifted signal strength scale or is below a low power threshold of the shifted signal strength scale.
Abstract:
A first node includes a first cache and a plurality of coherent agents. In response to a transaction to a coherency block by a first coherent agent of the plurality of coherent agents, the first node is configured to fetch the coherency block from another node. The other node is configured to record a state in which the coherency block is provided to the first node. The first cache is designated to store the state of the coherency block recorded by the first node.
Abstract:
A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.
Abstract:
A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication.
Abstract:
A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and a decoder. The feedforward equalizer comprises a non-adaptive filter and a gain stage. The non-adaptive filter receives the signal samples and produces a filtered signal. The gain stage adjusts the gain of the feedforward equalizer by adjusting the amplitude of the filtered signal. The amplitude of the filtered signal is adjusted so that it fits in the operational range of the decoder. The feedforward equalizer does not affect the sampling phase setting of the timing recovery module of the receiver.
Abstract:
A method for processing signals is disclosed and may include performing using one or more circuits in a multiband radio, functions including receiving an input signal from an oscillator that generates signals for each of a plurality of bands handled by the multiband radio. The received input signal may be divided. A feedback loop reference signal may be generated from the input signal. A coarse calibration signal and/or a fine calibration signal may be generated from the generated feedback loop reference signal. The oscillator may be calibrated utilizing the coarse calibration signal and/or the fine calibration signal. The input signal generated by the oscillator may be between about 3.4 GHz and 4 GHz. The receive input signal may be buffered. The generated feedback loop reference signal may also be buffered.
Abstract:
Certain aspects of a method and system for tuning an antenna using injection may include mixing a received DVB-H signal with a reference oscillator signal to generate an added DVB-H signal. A mixed signal may be generated from the added DVB-H signal using the reference oscillator signal. A wireless antenna that receives the received DVB-H signal may be tuned based on a received signal strength indicator (RSSI) associated with the mixed signal. The reference oscillator signal may be generated and then may be amplified. The first mixed DVB-H signal may be amplified prior to the generating of the mixed signal. The RSSI associated with the mixed signal may be determined. The tuning may occur during receiving of a preamble of a packet for the received DVB-H signal and/or during receiving of a plurality of packets for the received DVB-H signal.
Abstract:
Methods and systems for processing data are disclosed herein and may comprise receiving packetized data via at least one input port in an 802.1p and 802.1Q QoS compliant Ethernet switch integrated within a single gigabit Ethernet IP telephone chip that processes multiple voice channels. A priority class may be assigned by the 802.1p and 802.1Q compliant QoS Ethernet switch to at least a portion of the received packetized data. The received packetized data may be processed by the 802.1p and 802.1Q QoS compliant Ethernet switch based on the assigned priority class. The priority class may comprise a high priority class and/or a low priority class. If the priority class comprises a high priority class, the portion of the received packetized data may be buffered in a high priority buffer integrated within the 802.1p and 802.1Q QoS compliant Ethernet switch.
Abstract:
Methods and systems for processing signals in a receiver are disclosed herein and may include updating a plurality of filter taps utilizing at least one channel response vector and at least one correlation vector, for a plurality of received clusters, based on initialized values related to the at least one channel response vector and the at least one correlation vector. At least a portion of the received signal clusters may be filtered utilizing at least a portion of the updated plurality of filter taps. The update may be repeated whenever a specified signal-to-noise ratio (SNR) for the received signal clusters is reached. The initialized values may be updated during a plurality of iterations, and the update may be repeated whenever a specified number of the plurality of iterations is reached.
Abstract:
A system and method for packet processing are disclosed. The method may include performing using at least one processor, generating a DVB transport stream packet from a DSS transport stream packet. The generation may include mapping a prefix portion of a DSS transport stream packet into a header portion of the DVB transport stream packet comprising an inserted adaptation field. The inserted adaptation field may increase a size of the header portion of the DVB transport stream packet, and may decrease a size of a payload portion of the of the DVB transport stream. The generation may also include mapping a payload portion of the DSS transport stream packet into the payload portion of the DVB transport stream packet comprising the decreased size. The adaptation field may be at least fifty six (56) bytes in size.