公开(公告)号：US20240194253A1

公开(公告)日：2024-06-13

申请号：US18080456

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pirooz Parvarandeh ,  Venkatesh P. Gopinath ,  Navneet Jain ,  Bipul C. Paul ,  Halid Mulaosmanovic

IPC: G11C11/412 ,  G11C11/419 ,  H01L21/28 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104 ,  H01L29/40111

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

公开(公告)号：US20240186429A1

公开(公告)日：2024-06-06

申请号：US18062201

申请日：2022-12-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli ,  Ramsey M. Hazbun

IPC: H01L31/0224 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/18

CPC classification number: H01L31/022408 ,  H01L31/03125 ,  H01L31/1037 ,  H01L31/1812

Abstract: A photodiode and a related method of manufacture are disclosed. The photodiode includes a transfer gate and a floating diffusion adjacent to the transfer gate. In addition, the photodiode includes an upper terminal; an intrinsic semiconductor region in contact with the upper terminal, the intrinsic semiconductor region in a trench in a substrate adjacent to the transfer gate; and a lower terminal in contact with the intrinsic semiconductor region. An insulator layer is along an entirety of a sidewall of the intrinsic semiconductor region and between the intrinsic semiconductor region and the transfer gate. A p-type well may also optionally be between the insulator layer and the transfer gate.

公开(公告)号：US20240186240A1

公开(公告)日：2024-06-06

申请号：US18438916

申请日：2024-02-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkata Narayana Rao VANUKURU ,  Zhong-Xiang HE

IPC: H01L23/522 ,  H01F17/00 ,  H01F41/04 ,  H01L23/528

CPC classification number: H01L23/5227 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5283

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.

公开(公告)号：US20240184045A1

公开(公告)日：2024-06-06

申请号：US18076265

申请日：2022-12-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Arpan DASGUPTA ,  Norman W. ROBSON ,  Danny MOY

IPC: G02B6/125 ,  G02B6/12

CPC classification number: G02B6/125 ,  G02B6/12009

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an identification system, method of manufacture and method of use. The structure includes at least one waveguide structure and at least one damaged region positioned in a unique pattern on the at least one waveguide structure.

公开(公告)号：US20240176067A1

公开(公告)日：2024-05-30

申请号：US18058967

申请日：2022-11-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Ravi Prakash Srivastava

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/136 ,  H01L25/16

CPC classification number: G02B6/12004 ,  G02B6/1228 ,  G02B6/136 ,  H01L25/167

Abstract: Structures and methods implement an enlarged multilayer nitride waveguide. The structure may include an inter-level dielectric (ILD) layer over a substrate. A first enlarged multilayer nitride waveguide is positioned in the ILD layer in a region of the substrate. A second multilayer nitride waveguide may also be provided in the ILD layer. A lower cladding layer defines a lower surface of the nitride waveguide(s). The lower cladding layer has a lower refractive index than the nitride waveguide(s). Additional lower refractive index cladding layers can be provided on the upper surface and/or sidewalls of the nitride waveguide(s). The enlarged nitride waveguide may be implemented with other conventional silicon and nitride waveguides.

公开(公告)号：US20240172455A1

公开(公告)日：2024-05-23

申请号：US17990800

申请日：2022-11-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： John J. Pekarik ,  Hong Yu ,  Vibhor Jain ,  Alexander Derrickson ,  Venkatesh Gopinath

IPC: H01L47/00 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L27/2445 ,  H01L29/66242 ,  H01L29/7371 ,  H01L45/1233 ,  H01L45/16

Abstract: Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a substrate having a top surface, a trench isolation region in the substrate, and a base layer on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor includes a first collector in the substrate and a first emitter on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor includes a second collector in the substrate and a second emitter on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.

公开(公告)号：US20240170561A1

公开(公告)日：2024-05-23

申请号：US17990931

申请日：2022-11-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Jeffrey Johnson ,  Viorel Ontalus ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7378 ,  H01L29/0817 ,  H01L29/66242

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an emitter, a collector including a first section, a second section, and a third section positioned in a first direction between the first section and the second section, and an intrinsic base disposed in a second direction between the emitter and the third section of the collector. The structure further comprises a stress layer including a section positioned to overlap with the emitter, the intrinsic base, and the collector. The section of the stress layer is surrounded by a perimeter, and the first and second sections of the collector are each positioned adjacent to the perimeter of the stress layer.

公开(公告)号：US20240162146A1

公开(公告)日：2024-05-16

申请号：US17984724

申请日：2022-11-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh M. PANDEY ,  Rajendran KRISHNASAMY ,  Vibhor JAIN

IPC: H01L23/525

CPC classification number: H01L23/5256

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an e-fuse with metal fill structures and methods of manufacture. The structure includes: an insulator material; an e-fuse structure on the insulator material; a plurality of heaters on the insulator material and positioned on sides of the e-fuse structure; and conductive fill material within a space between the e-fuse structure and the plurality of heaters.

公开(公告)号：US11984160B2

公开(公告)日：2024-05-14

申请号：US17679207

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pirooz Parvarandeh ,  Periyapatna G. Venkatesh

IPC: G11C11/00 ,  G11C13/00 ,  H04L9/32

CPC classification number: G11C13/0059 ,  G11C13/004 ,  G11C13/0069 ,  H04L9/3278

Abstract: Circuits that include resistive memory elements and methods of using such circuits to generate a physical unclonable function. The circuit includes a first resistive memory element, a second resistive memory element, a first transistor having a source/drain region connected to the first resistive memory element, and a second transistor having a source/drain region connected to the second resistive memory element. The circuit further includes a first inverter having an input connected to a first node between the first transistor and the first resistive memory element, and a second inverter having an input connected to a second node between the second transistor and the second resistive memory element.

公开(公告)号：US20240145469A1

公开(公告)日：2024-05-02

申请号：US17974005

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh SHARMA ,  Johnatan A. KANTAROVSKY

IPC: H01L27/088 ,  H01L27/10 ,  H01L29/20

CPC classification number: H01L27/0883 ,  H01L27/101 ,  H01L29/2003

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a depletion mode device with a programmable element used for chip programming and circuit configuration and methods of manufacture and operation. In particular, the structure includes a programmable element on an active layer of semiconductor material, and a depletion mode device comprising a dual gate connected to the programmable element.