公开(公告)号：US07167052B2

公开(公告)日：2007-01-23

申请号：US10868145

申请日：2004-06-15

申请人： John D. Heightley ,  Jon Allan Faue

发明人： John D. Heightley ,  Jon Allan Faue

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2200/513 ,  H03F2203/45684

摘要： A differential amplifier design and bias control technique of particular applicability for low voltage operation in which the threshold voltage of n-channel differential input transistors is controlled using substrate bias in order to allow a wider range of input signal levels. Further disclosed is a technique for controlling the substrate bias of the input transistors of a differential amplifier based on the level of the output of the amplifier in addition to a differential amplifier circuit capable of low voltage operation in which an additional bias current is introduced that enables the output pull-up current to be increased without increasing the pull-down current, as well as circuitry for optimizing the performance of the differential in both DDR-I and DDR-II operational modes.

摘要翻译： 用于低电压操作的差分放大器设计和偏置控制技术，其中使用衬底偏置来控制n沟道差分输入晶体管的阈值电压，以便允许更宽范围的输入信号电平。 进一步公开了一种用于基于放大器的输出电平来控制差分放大器的输入晶体管的衬底偏置的技术，除了能够进行低电压操作的差分放大器电路之外，其中引入额外的偏置电流，使得能够 在不增加下拉电流的情况下增加输出上拉电流，以及用于优化DDR-I和DDR-II操作模式中的差分性能的电路。

公开(公告)号：US20070008784A1

公开(公告)日：2007-01-11

申请号：US11177537

申请日：2005-07-08

申请人： Jon Faue ,  Steve Eaton ,  Michael Murray

发明人： Jon Faue ,  Steve Eaton ,  Michael Murray

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/1096

摘要： A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

摘要翻译： 用于集成电路存储器的数据总线电路包括用于将存储器与I / O块连接的每个I / O焊盘的4位总线，但每个I / O仅使用两位用于写入。 使用四位每个I / O焊盘进行读取。 在输入数据选通的每个下降沿，最后两位通过总线发送，这样就不需要精确计数输入数据选通脉冲。 数据总线电路兼容DDR1和DDR2工作模式。

公开(公告)号：US07148104B2

公开(公告)日：2006-12-12

申请号：US10797972

申请日：2004-03-10

申请人： Yi Ding

发明人： Yi Ding

IPC分类号： H01L21/8247

CPC分类号： H01L29/42344 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11531

摘要： In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an dielectric (302, 304, 310) formed over control gate lines (134). Each control gate line provides control gates for one column of the memory cells. The adjacent control gate lines for the adjacent memory columns are spaced from each other. The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

摘要翻译： 在非易失性存储器中，选择栅极（144S）由一个导电层（例如多晶硅或多边形）形成，并且互连选择栅极的字线（144）由不同的导电层（例如金属）制成。 字线覆盖在控制栅线（134）上形成的电介质（302,304,310）。 每个控制栅极线提供一列存储器单元的控制栅极。 用于相邻存储器列的相邻控制栅极线彼此间隔开。 可以控制电介质厚度以减小字线和控制门之间的电容。 在一些实施例中，使用浮动栅极层的各向同性蚀刻，以自对准的方式制造浮置栅极（120）。

公开(公告)号：US20060234441A1

公开(公告)日：2006-10-19

申请号：US11222966

申请日：2005-09-12

申请人： Jung Wu Chien ,  Tsai Nieh ,  Ju Cheng Chen ,  Chao Hsi Chung

发明人： Jung Wu Chien ,  Tsai Nieh ,  Ju Cheng Chen ,  Chao Hsi Chung

IPC分类号： H01L21/465 ,  H01L21/8242

CPC分类号： H01L21/0273 ,  B82Y10/00 ,  H01L21/31116 ,  H01L21/31625 ,  H01L27/10861 ,  H01L28/84 ,  H01L29/66181

摘要： A method for preparing a deep trench first forms a trench in a semiconductor substrate and a stacked structure in the trench, wherein the stacked structure includes at least one nitrogen-containing layer. A phosphorous oxide layer is then formed on the surface of the nitrogen-containing layer. The phosphorous oxide is then transformed into an etchant in a steam atmosphere to remove the nitrogen-containing layer in the trench. The phosphorous oxide layer in the trench is then removed, and the nitrogen-containing layer can be effectively removed. The method further comprises forming a plurality of crystallites on a portion of the nitrogen-containing layer before the phosphorous oxide layer is formed on the surface of the nitrogen-containing layer, which allows the formation of a deep trench with a rough inner sidewall.

摘要翻译： 用于制备深沟槽的方法首先在半导体衬底中形成沟槽，并在沟槽中形成堆叠结构，其中堆叠结构包括至少一个含氮层。 然后在含氮层的表面上形成磷氧化物层。 然后将氧化磷在蒸汽气氛中转化成蚀刻剂以除去沟槽中的含氮层。 然后去除沟槽中的磷氧化物层，并且可以有效地去除含氮层。 该方法还包括在含氮层的表面上形成含氮层的一部分之前形成多个微晶，这允许形成具有粗糙内侧壁的深沟槽。

公开(公告)号：US07098100B1

公开(公告)日：2006-08-29

申请号：US11114152

申请日：2005-04-26

申请人： Hui Min Li ,  Jung Wu Chien ,  Chao Hsi Chung ,  Ming Hung Lin

发明人： Hui Min Li ,  Jung Wu Chien ,  Chao Hsi Chung ,  Ming Hung Lin

IPC分类号： H01L21/8234

CPC分类号： H01L29/66181 ,  H01L27/10861

摘要： The present invention discloses a trench capacitor formed in a trench in a semiconductor substrate. The trench capacitor comprises a bottom electrode positioned on a lower outer surface of the trench, a dielectric layer positioned on an inner surface of the bottom electrode, a top electrode positioned on the dielectric layer, a collar oxide layer positioned on an upper inner surface of the trench, a buried conductive strap positioned on the top electrode, and an interface layer made of silicon nitride positioned at the side of the buried conductive strap. The bottom electrode, the dielectric layer and the top electrode form a capacitive structure. The collar oxide layer includes a first block and a second block, and the height of the first block is larger than the height of the second block. The interface layer is positioned on a portion of the inner surface of the trench above the second block.

摘要翻译： 本发明公开了一种在半导体衬底的沟槽中形成的沟槽电容器。 所述沟槽电容器包括位于所述沟槽的下外表面上的底电极，位于所述底电极的内表面上的电介质层，位于所述电介质层上的顶电极，位于所述电介质层的上内表面上的环状氧化物层 沟槽，位于顶部电极上的埋入导电带，以及位于掩埋导电带侧面的由氮化硅制成的界面层。 底部电极，电介质层和顶部电极形成电容结构。 环状氧化物层包括第一块和第二块，并且第一块的高度大于第二块的高度。 界面层位于第二块上方的沟槽的内表面的一部分上。

公开(公告)号：US07057231B2

公开(公告)日：2006-06-06

申请号：US10847850

申请日：2004-05-17

申请人： Yi Ding ,  Vei-Han Chan

发明人： Yi Ding ,  Vei-Han Chan

IPC分类号： H01L21/8238

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825

摘要： A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell's floating gate transistor has a first source/drain region (226), a channel region (224), and a second source/drain region (130). The dielectric (128) is stronger against leakage near at least a portion of the first source/drain region (122) than near at least a portion of the channel region. The stronger portion (128.1) of the additional dielectric improves data retention without increasing the programming and erase times if the programming and erase operations do not rely on a current through the stronger portion. Additional dielectric (210) has a portion located below the top surface of the substrate between the trench and a top part of the second source/drain region (130). The second source/drain region has a part located below the additional dielectric and meeting the trench. The additional dielectric can be formed with shallow trench isolation technology. The additional dielectric reduces the capacitance between the second source/drain region (130) and the floating gate.

公开(公告)号：US07057191B2

公开(公告)日：2006-06-06

申请号：US10966595

申请日：2004-10-14

申请人： Heng-Kai Hsu ,  Yu-Chi Chen

发明人： Heng-Kai Hsu ,  Yu-Chi Chen

IPC分类号： G21K5/10 ,  H01J37/08

CPC分类号： H01J37/3171 ,  H01J2237/004 ,  H01J2237/18 ,  H01J2237/31703 ,  H01J2237/31705

摘要： A method of controlling the implant dosage is provided. First, the residual gases within an ion implant station are analyzed and the partial pressure of each residual gas is measured. Thereafter, the current Im of the ion beam is measured and the real dosage Ir of the ion beam implanted into a wafer is calculated. Since all the residual gases in the ion implant station are considered, the implanting dosage can be accurately controlled.

摘要翻译： 提供了一种控制种植体剂量的方法。 首先，分析离子注入站内的残留气体，并测量每个残留气体的分压。 此后，测量离子束的电流Im，并计算注入到晶片中的离子束的实际剂量Ir。 由于考虑了离子注入站中的所有残留气体，因此可以精确地控制植入剂量。

公开(公告)号：US20060086963A1

公开(公告)日：2006-04-27

申请号：US11234276

申请日：2005-09-26

申请人： Hsiao Wu

发明人： Hsiao Wu

IPC分类号： H01L29/94

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

摘要： The present invention discloses a stacked capacitor having interdigital electrodes and method for preparing the same. The stacked capacitor comprises a first interdigital electrode, a second interdigital electrode and a dielectric material sandwiched between the first interdigital electrode and the second interdigital electrode. The first and the second interdigital electrodes comprise a body and a plurality of fingers electrically connected to the body, and the dielectric material can be silicon nitride or silicon oxide. Preferably, fingers of the first interdigital electrode are made of titanium nitride, while fingers of the second interdigital electrode are made of polysilicon. The body of the first and the second interdigital electrodes are preferably made of titanium nitride.

公开(公告)号：US20060057848A1

公开(公告)日：2006-03-16

申请号：US10979161

申请日：2004-11-03

申请人： Meng Cheng ,  Ya Ling Po ,  Ting Sing Wang

发明人： Meng Cheng ,  Ya Ling Po ,  Ting Sing Wang

IPC分类号： H01L21/302

CPC分类号： H01L29/66181 ,  H01L21/30604 ,  H01L21/30608 ,  H01L27/1087

摘要： The method for preparing a deep trench uses a dry etching process to form a trench in a silicon substrate, and an etching mixture is then coated on the surface of the silicon substrate and inside the deep trench. A portion of etching mixture is removed from the surface of the silicon substrate and the trench above a predetermined depth from the surface of the substrate, and an etching process is then performed using the etching mixture remaining inside the trench to etch the silicon substrate below the predetermined depth so as to form the deep trench. The etching mixture comprises a conveying solution and an etchant, and the viscosity of the conveying solution is higher than that of the etchant. The conveying solution is spin-on-glass or a photoresist, and the etchant is tetramethylammonium hydroxide, ammonium, or hydrofluoric acid. The volume ratio of the conveying solution and the etchant is preferably between 50:1 and 20:1.

公开(公告)号：US07001810B2

公开(公告)日：2006-02-21

申请号：US10769025

申请日：2004-01-30

申请人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen

IPC分类号： H01L21/336 ,  H01L21/26

CPC分类号： H01L29/66825 ,  H01L21/28273

摘要： The floating gate, or the oxide between the floating and control gates, or both are nitrided before the control gate layer is deposited.