公开(公告)号：US20070170481A1

公开(公告)日：2007-07-26

申请号：US11717145

申请日：2007-03-13

申请人： Hee Kang ,  Jin Ahn ,  Jae Lee

发明人： Hee Kang ,  Jin Ahn ,  Jae Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

摘要： A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

摘要翻译： 提供非易失性铁电存储器件，以便使用由铁电材料的极性状态区分的存储单元的沟道电阻来控制非易失性存储单元的读/写操作。 在存储器件中，在底部字线上形成绝缘层，并且在绝缘层上形成包括N型漏极区，P型沟道区和N型源极区的浮动沟道层。 然后，在浮动沟道层上形成铁电体层，在铁电体层上形成字线。 结果，根据铁电层的极性来控制感应到沟道区的电阻状态，从而调节存储单元阵列的读/写操作。

公开(公告)号：US07164166B2

公开(公告)日：2007-01-16

申请号：US10804795

申请日：2004-03-19

申请人： Mark S. Isenberger ,  Ebrahim Andideh

发明人： Mark S. Isenberger ,  Ebrahim Andideh

IPC分类号： H01L29/76

CPC分类号： H01L27/11585 ,  H01L27/115 ,  H01L27/1159 ,  H01L29/78391

摘要： A memory circuit is provided with a spacer formed on a support surface and positioned adjacent to a first electrode surface of a first electrode. The memory circuit further includes a ferroelectric layer formed on the first electrode and the spacer.

摘要翻译： 存储器电路设置有形成在支撑表面上并且邻近第一电极的第一电极表面定位的间隔件。 存储电路还包括形成在第一电极和间隔物上的铁电层。

公开(公告)号：US07153706B2

公开(公告)日：2006-12-26

申请号：US10829053

申请日：2004-04-21

申请人： Sanjeev Aggarwal ,  Kelly J. Taylor ,  Lindsey Hall ,  Satyavolu Srinivas Papa Rao

发明人： Sanjeev Aggarwal ,  Kelly J. Taylor ,  Lindsey Hall ,  Satyavolu Srinivas Papa Rao

IPC分类号： H01L21/00

CPC分类号： H01L27/11585 ,  H01L21/31053 ,  H01L27/11502 ,  H01L27/1159 ,  H01L28/55

摘要： The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).

摘要翻译： 本发明提供一种铁电电容器及其制造方法，以及制造铁电随机存取存储器（FeRAM）器件的方法。 除了其他元件之外，铁电电容器（100）包括位于第一电极层（160）上方的基本平坦的铁电介质层（165），其中基本上平坦的铁电介质层（165）的平均表面粗糙度小于约 4nm。 铁电电容器（100）还包括位于基本上平坦的铁电介质层（165）上方的第二电极层（170）。

公开(公告)号：US07053433B1

公开(公告)日：2006-05-30

申请号：US10135488

申请日：2002-04-29

申请人： Gary F. Derbenwick

发明人： Gary F. Derbenwick

IPC分类号： H01L27/108

CPC分类号： H01L27/1159 ,  H01L27/11502 ,  H01L27/11585

摘要： A ferroelectric layer within an array of ferroelectric FETs is encapsulated between a bottom barrier dielectric layer and a top barrier dielectric layer extending beyond the ferroelectric layer. The ferroelectric FETs are formed on first conductivity type silicon, each having two second conductivity type silicon regions within the first conductivity type silicon separated by some distance. The two second conductivity type silicon regions forming a source and a drain with a channel region therebetween. A silicon dioxide layer is formed on the channel region, a bottom barrier dielectric layer is formed on the silicon dioxide layer, a ferroelectric layer is formed on the bottom barrier dielectric layer, a top barrier dielectric layer is formed on the ferroelectric layer, and an electrode layer is formed on the ferroelectric layer.

摘要翻译： 铁电FET阵列内的铁电层被封装在底部阻挡介电层和延伸超出铁电层的顶部阻挡介电层之间。 铁电FET形成在第一导电型硅上，每个第一导电类型的硅在第一导电类型硅内部具有两个第二导电类型的硅区域，分隔一定距离。 两个第二导电类型的硅区域形成在其间具有沟道区域的源极和漏极。 在沟道区上形成二氧化硅层，在二氧化硅层上形成底部阻挡介电层，在底部阻挡介电层上形成铁电体层，在铁电体层上形成顶部阻挡介电层， 在铁电体层上形成电极层。

公开(公告)号：US20060073614A1

公开(公告)日：2006-04-06

申请号：US11102921

申请日：2005-04-11

申请人： Kousuke Hara

发明人： Kousuke Hara

IPC分类号： H01L21/00

CPC分类号： H01L27/11502 ,  H01L21/31116 ,  H01L21/76895 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/57 ,  H01L28/60

摘要： The present invention provides a ferroelectric capacitor structure comprising a ferroelectric capacitor which is constituted in such a manner that a lower electrode is formed, a ferroelectric film is formed on the lower electrode and an upper electrode is formed on the ferroelectric film, and which is formed in a predetermined pattern; a hydrogen diffusion barrier film formed on the ferroelectric capacitor; an interlayer insulating film formed on the hydrogen diffusion barrier film; and a contact hole for connecting the upper electrode and an upper metal wiring layer. In the ferroelectric capacitor structure, etching of the interlayer insulating film is performed using a gas containing a fluorine element, and etching of the hydrogen diffusion barrier film is carried out using a mixed gas of at least a gas containing a reductive group and a halogen gas, or a halogen gas having a reductive group as a constituent substance.

摘要翻译： 本发明提供一种强电介质电容器结构，其特征在于，具有铁电电容器，该铁电电容器以下电极形成的方式构成，在所述下电极上形成有铁电体膜，在所述强电介质膜上形成上电极，形成 以预定图案; 形成在强电介质电容器上的氢扩散阻挡膜; 形成在所述氢扩散阻挡膜上的层间绝缘膜; 以及用于连接上电极和上金属布线层的接触孔。 在铁电电容器结构中，使用含有氟元素的气体进行层间绝缘膜的蚀刻，使用至少含有还原基团和卤素气体的气体的混合气体进行氢扩散阻挡膜的蚀刻 或具有还原性基团的卤素气体作为构成物质。

公开(公告)号：US20060003472A1

公开(公告)日：2006-01-05

申请号：US11215778

申请日：2005-08-30

申请人： Vishnu Agarwal ,  Howard Rhodes

发明人： Vishnu Agarwal ,  Howard Rhodes

IPC分类号： H01L21/00 ,  H01L29/76 ,  H01L21/8242

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

摘要： Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.

公开(公告)号：US20050218443A1

公开(公告)日：2005-10-06

申请号：US11089432

申请日：2005-03-24

申请人： Hiroaki Tamura ,  Teruo Tagawa

发明人： Hiroaki Tamura ,  Teruo Tagawa

IPC分类号： H01L27/105 ,  G11C11/22 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/1159 ,  H01L27/11502 ,  H01L27/11585 ,  H01L28/57

摘要： A ferroelectric capacitor is covered with a hydrogen barrier film, and an inner wall of a contact hole provided above an upper electrode of the ferroelectric capacitor is also covered with a hydrogen barrier film, thereby preventing hydrogen from infiltrating in the ferroelectric capacitor through a contact hole.

摘要翻译： 铁电电容器被氢阻挡膜覆盖，并且设置在铁电电容器的上电极上方的接触孔的内壁也被氢阻挡膜覆盖，从而防止氢通过接触孔渗入铁电电容器 。

公开(公告)号：US20050128816A1

公开(公告)日：2005-06-16

申请号：US11043485

申请日：2005-01-26

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

IPC分类号： H01L21/8247 ,  G11C11/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L31/0328

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L21/28291 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11568 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/42332 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/792

摘要： Floating trap non-volatile memory devices and methods are provided. The memory devices include a semiconductor substrate and an adjacent gate electrode. Between the substrate and the gate electrode may be a tunneling insulating layer having a first dielectric constant, a blocking insulating layer having a second dielectric constant that is greater than the first dielectric constant, and a charge storage layer.

公开(公告)号：US20050090023A1

公开(公告)日：2005-04-28

申请号：US10946289

申请日：2004-09-22

申请人： Haochieh Liu

发明人： Haochieh Liu

IPC分类号： G11C11/22 ,  H01L21/00 ,  H01L21/82 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L27/11585 ,  H01L27/1159

摘要： A MFMIS memory device is provided with an inverted T-shaped gate stack, which is formed using only one word line mask. The MFMIS memory device is formed using one word line mask, which forms the word line, and using spacers to form an inverted T-shaped gate stack, which is compatible with self-aligned etch processes.

摘要翻译： MFMIS存储器件设置有仅使用一个字线掩模形成的倒置的T形栅极堆叠。 MFMIS存储器件使用形成字线的一个字线掩模形成，并且使用间隔件形成与自对准蚀刻工艺兼容的反向T形栅极叠层。

公开(公告)号：US20050087831A1

公开(公告)日：2005-04-28

申请号：US10986778

申请日：2004-11-15

申请人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Katsuyuki Sekine ,  Yuji Saito

发明人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Katsuyuki Sekine ,  Yuji Saito

IPC分类号： H01L21/316 ,  G11C11/16 ,  H01L21/28 ,  H01L21/318 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/12 ,  H01L29/04 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/788 ,  H01L29/00

CPC分类号： H01L21/28185 ,  G11C11/16 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28238 ,  H01L21/28291 ,  H01L27/11521 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/7883

摘要： A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.

摘要翻译： 半导体器件包括在（111）表面附近具有晶体表面的Si晶体和形成在所述晶体表面上的绝缘膜，所述绝缘膜的至少一部分包括含有Kr或Si氮化物的Si氧化物膜 含Ar或Kr的薄膜。