公开(公告)号：US07272177B2

公开(公告)日：2007-09-18

申请号：US10687671

申请日：2003-10-20

Applicant: Hou-Wei Lin ,  Shieh-Hsing Kuo ,  Meng-Han Hsieh ,  Kuang-Yu Yen

Inventor： Hou-Wei Lin ,  Shieh-Hsing Kuo ,  Meng-Han Hsieh ,  Kuang-Yu Yen

IPC: H03H7/30

CPC classification number: H04L25/03038 ,  H03H21/0012 ,  H04L7/0062 ,  H04L25/03235 ,  H04L2025/03363 ,  H04L2025/03477

Abstract: A transceiver of a communication system is disclosed. The transceiver comprises a front-end receiver for receiving a receiving signal and converting to a first signal with a pre-cursor component and a post-cursor component, a noise canceller coupled to the front-end receiver 10 for generating a second signal through eliminating the noise of the first signal, a Feed-Forward Equalizer (FFE) coupled to the noise canceller for generating a third signal through eliminating the pre-cursor component in the second signal according to a transfer function including a plurality of adjustable constants, wherein the adjustable constants includes a main-tap and the value of the main-tap is predetermined, and a decoding system coupled to the FFE for decoding the third signal and eliminating the post-cursor component in the third signal.

Abstract translation: 公开了一种通信系统的收发器。 收发器包括前端接收器，用于接收接收信号并用前置光标分量和后光标分量转换成第一信号;噪声消除器，耦合到前端接收机10，用于通过消除产生第二信号 第一信号的噪声，耦合到噪声消除器的前馈均衡器（FFE），用于通过根据包括多个可调常数的传递函数消除第二信号中的前置分量来产生第三信号，其中， 可调常数包括主抽头，并且主抽头的值是预定的，以及耦合到FFE的解码系统，用于解码第三信号并消除第三信号中的后标光分量。

公开(公告)号：US20070195875A1

公开(公告)日：2007-08-23

申请号：US11688669

申请日：2007-03-20

Applicant: Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

Inventor： Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

IPC: H03H7/30 ,  H03D1/00

CPC classification number: H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Abstract translation: 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US20070104262A1

公开(公告)日：2007-05-10

申请号：US11616630

申请日：2006-12-27

Applicant: Stuart Sandberg ,  Arnon Friedmann ,  Jelena Jovin ,  Bindu Chandna

Inventor： Stuart Sandberg ,  Arnon Friedmann ,  Jelena Jovin ,  Bindu Chandna

IPC: H03K5/159 ,  H04K1/10 ,  H04B1/10 ,  H04B3/20

CPC classification number: H04L25/03038 ,  H04L25/03019 ,  H04L2025/03414 ,  H04L2025/03477 ,  H04L2025/03611 ,  H04L2025/03617 ,  H04L2025/03764 ,  H04L2025/0377

Abstract: Using a known or later developed time domain equalizer coefficient training algorithm, a least square solution for the time domain equalizer coefficients is taken at a starting point and iteratively improved on. In particular, the improvement is directed towards maximizing number of bits per frame loaded over the time domain equalizer coefficient choice. This can be accomplished by maximizing capacity directly rather than setting a goal to shorten the channel and hoping that the capacity will be maximized as a result.

Abstract translation: 使用已知或稍后开发的时域均衡器系数训练算法，在起点进行时域均衡器系数的最小二乘解，迭代改进。 特别地，改进旨在通过时域均衡器系数选择来最大化每帧加载的比特数。 这可以通过直接最大化容量来实现，而不是设定缩短通道的目标，并希望能力最大化。

公开(公告)号：US07197069B2

公开(公告)日：2007-03-27

申请号：US10680929

申请日：2003-10-08

Applicant: Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

Inventor： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC classification number: H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Abstract translation: 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US07180938B2

公开(公告)日：2007-02-20

申请号：US09982065

申请日：2001-10-19

Applicant: Stuart D Sandberg ,  Arnon Friedmann ,  Jelena Jovin ,  Bindu Chandna

Inventor： Stuart D Sandberg ,  Arnon Friedmann ,  Jelena Jovin ,  Bindu Chandna

IPC: H03H7/30

CPC classification number: H04L25/03038 ,  H04L25/03019 ,  H04L2025/03414 ,  H04L2025/03477 ,  H04L2025/03611 ,  H04L2025/03617 ,  H04L2025/03764 ,  H04L2025/0377

Abstract: Using a known or later developed time domain equalizer coefficient training algorithm, a least square solution for the time domain equalizer coefficients is taken at a starting point and iteratively improved on. In particular, the improvement is directed towards maximizing number of bits per frame loaded over the time domain equalizer coefficient choice. This can be accomplished by maximizing capacity directly rather than setting a goal to shorten the channel and hoping that the capacity will be maximized as a result.

Abstract translation: 使用已知或稍后开发的时域均衡器系数训练算法，在起点进行时域均衡器系数的最小二乘解，迭代改进。 特别地，改进旨在通过时域均衡器系数选择来最大化每帧加载的比特数。 这可以通过直接最大化容量来实现，而不是设定缩短通道的目标，并希望能力最大化。

公开(公告)号：US07116705B2

公开(公告)日：2006-10-03

申请号：US11210591

申请日：2005-08-24

Applicant: Jung-Lin Pan

Inventor： Jung-Lin Pan

IPC: H04B1/69 ,  H04B7/216

CPC classification number: H04B1/70757 ,  H04B1/707 ,  H04B1/7115 ,  H04B2201/70707 ,  H04L25/03038 ,  H04L2025/03375 ,  H04L2025/03477 ,  H04L2025/03617

Abstract: A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.

公开(公告)号：US07110448B2

公开(公告)日：2006-09-19

申请号：US10281784

申请日：2002-10-28

Applicant: Johannes Wilhelmus Maria Bergmans ,  Charalampos Pozidis ,  Jianjiang Wang

Inventor： Johannes Wilhelmus Maria Bergmans ,  Charalampos Pozidis ,  Jianjiang Wang

IPC: H03H7/30 ,  H04L27/06

CPC classification number: H04L7/0062 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/1403 ,  H04L7/0029 ,  H04L25/03038 ,  H04L2025/03477 ,  H04L2025/03624

Abstract: The invention concerns an asynchronous receiver for digital transmission and recording systems. The receiver comprises a sampling rate converter (SRC) for timing recovery, preceded by a digital adaptive equalizer operating at the sampling rate 1/Ts, asynchronous to the data rate 1/T. An equalizer adaptation method using zero-forcing (ZF) techniques is described for adapting equalizer taps asynchronously to the data rate via a control loop. To this end, the control loop comprises temporal interpolation means performing time-base conversion for converting signals from the synchronous domain (1/T) to the asynchronous domain (1/Ts) and spatial conversion means to convert T-spaced signals into Ts-spaced signals.

公开(公告)号：US20060182204A1

公开(公告)日：2006-08-17

申请号：US11402676

申请日：2006-04-12

Applicant: Douglas Cairns ,  Gregory Bottomley

Inventor： Douglas Cairns ,  Gregory Bottomley

IPC: H04L27/06

CPC classification number: H04L25/03044 ,  H04B1/7117 ,  H04B1/712 ,  H04B2201/70707 ,  H04B2201/709727 ,  H04L2025/03477 ,  H04L2025/03515

Abstract: A receiver includes a baseband processor for selecting a set of demodulation processing delays for received signal demodulation from a larger set of candidate delays. In one embodiment, the baseband processor selects the set of demodulation processing delays by calculating at least one metric for each demodulation processing delay in the set of candidate delays, iteratively reducing the set of candidate delays by eliminating one or more demodulation processing delays from the set as a function of comparing the metrics, and setting the processing delays for received signal demodulation to the candidate delays remaining after reduction. In a Generalized RAKE (G-RAKE) embodiment, the metric corresponds to combining weight magnitudes associated with G-RAKE finger delays. In a chip equalizer embodiment, the metric corresponds to coefficient magnitudes associated with equalization filter tap delays. In other embodiments, the metric corresponds to Signal to Interference Ratios (SIRs) associated with the set of candidate delays.

Abstract translation: 接收机包括基带处理器，用于从更大的一组候选延迟中选择用于接收信号解调的一组解调处理延迟。 在一个实施例中，基带处理器通过针对候选延迟集合中的每个解调处理延迟计算至少一个度量来选择一组解调处理延迟，通过从集合中消除一个或多个解调处理延迟来迭代地减少候选延迟集合 作为比较度量的函数，以及将接收信号解调的处理延迟设置为在还原之后剩余的候选延迟。 在广义RAKE（G-RAKE）实施例中，度量对应于与G-RAKE手指延迟相关联的重量幅度。 在码片均衡器实施例中，度量对应于与均衡滤波器抽头延迟相关联的系数幅度。 在其他实施例中，度量对应于与该组候选延迟相关联的信号与干扰比（SIR）。

公开(公告)号：US07058150B2

公开(公告)日：2006-06-06

申请号：US09844441

申请日：2001-04-30

Applicant: Aaron W. Buchwald ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

Inventor： Aaron W. Buchwald ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC: H04L7/00

CPC classification number: H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

公开(公告)号：US07012983B2

公开(公告)日：2006-03-14

申请号：US09844296

申请日：2001-04-30

Applicant: Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

Inventor： Aaron W. Buchwald ,  Myles Wakayama ,  Michael Le ,  Jurgen Van Engelen ,  Xicheng Jiang ,  Hui Wang ,  Howard A. Baumer ,  Avanindra Madisetti

IPC: H03D3/34 ,  H04L7/00

CPC classification number: H04L25/03885 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0274 ,  H04L7/0337 ,  H04L25/03006 ,  H04L2025/03477 ,  H04L2025/03617

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.