公开(公告)号：US09245200B2

公开(公告)日：2016-01-26

申请号：US14068437

申请日：2013-10-31

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Luca Magri ,  Beatrice Rossi ,  Subarna Tripathi ,  Pasqualina Fragneto ,  Emiliano Mario Piccinelli

IPC: G06K9/46 ,  G06T7/00

CPC classification number: G06K9/4604 ,  G06T7/13 ,  G06T2207/20061

Abstract: An embodiment is a computer-implemented method for detecting a straight line in a digital image comprising a plurality of pixels comprising the steps: detecting an edge in the digital image, generating a first straight line which passes through a first pixel of the detected edge, generating a second straight line which passes through a second pixel of the detected edge, which is different from the first pixel, determining at least two intersections with a boundary of the digital image for each generated straight line, determining a set of two parameter values for each generated straight line based on the respective determined at least two intersections, wherein the set of two parameter values uniquely determines the respective generated straight line, and detecting the straight line in the digital image based on the determined sets of two parameter values.

Abstract translation: 一个实施例是用于检测包括多个像素的数字图像中的直线的计算机实现的方法，包括以下步骤：检测数字图像中的边缘，生成穿过检测到的边缘的第一像素的第一直线， 产生穿过所检测的边缘的不同于第一像素的第二像素的第二直线，为每个生成的直线确定与数字图像的边界的至少两个交点，确定一组两个参数值，以供 每个生成的直线基于相应确定的至少两个交点，其中所述两个参数值的集合唯一地确定相应生成的直线，并且基于所确定的两个参数值的集合来检测数字图像中的直线。

公开(公告)号：US09234938B2

公开(公告)日：2016-01-12

申请号：US14270964

申请日：2014-05-06

Applicant: STMicroelectronics International N.V.

Inventor： Shray Khullar ,  Swapnil Bahl

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/28

CPC classification number: G01R31/31727 ,  G01R31/2815 ,  G01R31/31704 ,  G01R31/31705 ,  G01R31/3177 ,  G01R31/318552 ,  G01R31/318594

Abstract: The On-Chip Clock (OCC) circuit is for testing an integrated circuit having logic blocks connected in scan chains. An OCC controller is configured to receive a plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals including at least two consecutive at-speed capture clock pulses. An OCC monitor is configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses. The OCC monitor may include a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses, a counter configured to count differences between the delayed pulses, and an output register coupled to the counter and configured to provide a static data verification (e.g. output on an integrated circuit pad) for the test engineer.

Abstract translation: 片内时钟（OCC）电路用于测试具有连接在扫描链中的逻辑块的集成电路。 OCC控制器被配置为接收多个时钟信号并输出​​多个移位/捕获时钟信号以供逻辑块的扫描链使用，所述多个移位/捕获时钟信号包括至少两个连续的低速捕获时钟 脉冲。 OCC监视器被配置为基于至少两个连续的在线捕获时钟脉冲来提供对OCC操作的验证。 OCC监视器可以包括多个寄存器，其被配置为基于至少两个连续的在线捕获时钟脉冲提供延迟的脉冲，配置为对延迟的脉冲之间的差异进行计数的计数器，以及耦合到计数器的输出寄存器，并被配置为 为测试工程师提供静态数据验证（例如集成电路板上的输出）。

公开(公告)号：US09231627B2

公开(公告)日：2016-01-05

申请号：US14072898

申请日：2013-11-06

Applicant: STMicroelectronics International N.V.

Inventor： Patrik Arno

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H03F1/0238 ,  H03F1/3241 ,  H03F1/3247 ,  H03F1/3258 ,  H03F3/19 ,  H03F3/24 ,  H03F2200/102 ,  H03F2200/336 ,  H03F2200/504 ,  H03F2201/3212 ,  H03F2201/3233 ,  H04B2001/0425

Abstract: The output of a Radio Frequency (RF) Power Amplifier (PA) is sampled and down-converted, and the amplitude envelope of the baseband feedback signal is extracted. This is compared to the envelope of a transmission signal, and the envelope tracking modulation of the RF PA supply voltage VCC is adaptively pre-distorted to achieve a constant ISO-Gain (and phase) in the RF PA. In particular, a nonlinear function is interpolated from a finite number gain values calculated from the feedback and transmission signals. This nonlinear function is then used to pre-distort the transmission signal envelope, resulting in a constant gain at the RF PA over a wide range of supply voltage VCC values. Since the gains are calculated from a feedback signal, the pre-distortion may be recalculated at event triggers, such as an RF frequency change. Furthermore, the method improves nonlinearity in the entire transmitter chain, not just the RF PA.

Abstract translation: 对射频（RF）功率放大器（PA）的输出进行采样和下变频，并提取基带反馈信号的幅度包络。 将其与传输信号的包络进行比较，并且RF PA电源电压VCC的包络跟踪调制被自适应地预失真以在RF PA中实现恒定的ISO增益（和相位）。 特别地，从反馈和传输信号计算的有限数量的增益值内插非线性函数。 然后使用这种非线性函数对传输信号包络进行预失真，从而在宽范围的电源电压VCC值下在RF PA上产生恒定的增益。 由于根据反馈信号计算增益，所以可以在诸如RF频率变化的事件触发时重新计算预失真。 此外，该方法改善了整个发射机链中的非线性，而不仅仅是RF PA。

公开(公告)号：US09209935B2

公开(公告)日：2015-12-08

申请号：US14337406

申请日：2014-07-22

Applicant: STMicroelectronics International N.V.

Inventor： Achraf Dhayni ,  Hussein Hijazi

IPC: H04B7/04 ,  H04L1/06 ,  H04L1/00 ,  H04L25/03

CPC classification number: H04L1/0054 ,  H04B7/0413 ,  H04L1/0631 ,  H04L25/03197 ,  H04L25/03242 ,  H04L25/03961 ,  H04L2025/03414 ,  H04L2025/0342 ,  H04L2025/03426

Abstract: A receiver estimates a vector of emitted symbols over a MIMO transmission channel which are emitted by a emitting antennas. The receiver receives a vector of received symbols on receiving antennas. Estimation of the vector of emitted symbols is made by calculating a metric associated with a criterion for each vector of a subset of all possible vectors of emitted symbols and selecting an estimation for said vector of emitted symbol as the vector of emitted symbols among said subset which minimizes said metric.

Abstract translation: 接收机估计由发射天线发射的MIMO传输信道上发射码元的向量。 接收机在接收天线上接收接收符号的向量。 通过计算与发射符号的所有可能向量的子集的每个向量的标准相关联的度量来估计发射符号的矢量，并且将所发射的符号的所述向量的估计选择为所述子集中的发射符号的向量， 最小化所述度量。

公开(公告)号：US20150341017A1

公开(公告)日：2015-11-26

申请号：US14283043

申请日：2014-05-20

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin GUPTA ,  Paramjeet Singh SAHNI ,  Tapas NANDY ,  Manish GARG

IPC: H03K3/01 ,  H04N5/63 ,  H04N5/44

CPC classification number: H03K3/01 ,  H03K19/018528 ,  H04N5/44 ,  H04N5/63

Abstract: A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.

Abstract translation: 功率收集电路包括新的发射机拓扑结构，其确保形成功率收集电路的薄氧化物晶体管的结不会经受超过最大可容忍结电压的晶体管结的电压。 补充供电电路用于在从接收器电路收集的功率不足以对发射机电路的这些组件充分供电时，向发射机电路中的组件提供补充馈电电流，这可能在耦合发射机的通信信道的高频操作期间发生 和接收器电路。 当从接收器电路收集的功率大于为发射机电路中的组件供电所需的功率时，辅助馈电电路还用于吸收分流电流。

公开(公告)号：US20150331985A1

公开(公告)日：2015-11-19

申请号：US14279587

申请日：2014-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Vishal Kumar Sharma ,  Manoj Sharma Kumar

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077

Abstract: A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area.

Abstract translation: 用于设计驱动器布局的计算机化方法包括分析原理图电路。 耦合在第一公共节点之间的PMOSFET被分组成一个或多个第一类。 耦合在第二公共节点之间的NMOSFET被分组成一个或多个第二类。 该方法还包括通过生成包括主MOSFET PCELL和主保护环PCELL的超参数化单元（PCELL）布局块来为驱动器的布局区域中的每个位置处的每个MOSFET生成布局，用于第一类和 二等。 主MOSFET PCELL包括MOSFET的第一组参数，主保护环PCELL包括围绕MOSFET的保护环的第二组参数。 主MOSFET PCELL和主保护环PCELL的子PCELL在布局区域的每个位置实例化。

公开(公告)号：US09165642B2

公开(公告)日：2015-10-20

申请号：US13746395

申请日：2013-01-22

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/08 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/418

Abstract: A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor. The wordline driver generates control signals on the true and complement wordlines to access the memory cell by: actuating the first access transistor while the second access transistor is not actuated and then actuating the second access transistor while the first access transistor is not actuated. The bitlines and wordlines are supplied from different sets of power supply voltages, with the bitline high supply voltage being less than the wordline high supply voltage.

Abstract translation: 存储单元包括具有真实数据节点和补码数据节点的锁存器，真位线，补码位线，耦合在真位线和真数据节点之间的第一存取晶体管，以及耦合在补码位线 和补码数据节点。 字线驱动器电路包括耦合以控制第一存取晶体管的真字字线和耦合以控制第二存取晶体管的补码字线。 字线驱动器通过在第二存取晶体管未被致动的同时致动第一存取晶体管，然后在第一存取晶体管未被致动时致动第二存取晶体管，在真和补码字线上产生访问存储单元的控制信号。 位线和字线由不同的电源电压供应，位线高电源电压小于字线高电源电压。

公开(公告)号：US20150280716A1

公开(公告)日：2015-10-01

申请号：US14231939

申请日：2014-04-01

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Sameer Vashishtha ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/0948 ,  H03K19/0185 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K19/09487 ,  H03K19/0027 ,  H03K19/00361 ,  H03K19/018521

Abstract: A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

Abstract translation: 缓冲器包括被配置为接收具有分别被引用到第一供电域的第一高电压和第一低电压的第一和第二逻辑状态的第一数字信号的输入。 第一反相器电路包括具有连接到输入的栅极端子的pMOS晶体管和nMOS晶体管。 第二反相器与第一反相器的输出串联。 第二反相器具有被配置为产生具有第一和第二逻辑状态的第二数字信号的第二数字信号，第一和第二逻辑状态分别被称为第二高电压和第二不同供电域的第二低电压，其中至少第二高电压是 大于第一高电压。 反馈电路被配置为将第二数字信号作为偏置施加到第一反相器电路的p-MOS晶体管的晶体管本体。

公开(公告)号：US20150280714A1

公开(公告)日：2015-10-01

申请号：US14231447

申请日：2014-03-31

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vinod KUMAR

IPC: H03K19/0185 ,  H03K3/3562

CPC classification number: H03K19/0185 ,  H03K3/35613 ,  H03K3/356165

Abstract: A level shifter circuit is configured to receive first and second complementary input signals. Each of the first and second complementary input signals have a value of either a first supply voltage or a first reference voltage. The level shifter further includes a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second output signals to a second supply voltage and includes a weak latch circuit operable to drive the other of the first and second output signals to a second reference voltage.

Abstract translation: 电平移位器电路被配置为接收第一和第二互补输入信号。 第一和第二互补输入信号中的每一个具有第一电源电压或第一参考电压的值。 电平移位器还包括强锁存电路，其可响应于第一和第二互补输入信号而工作，以将第一和第二输出信号中的一个驱动到第二电源电压，并包括可操作以驱动第一和第二输出信号中的另一个的弱锁存电路 输出信号到第二参考电压。

公开(公告)号：US09148099B2

公开(公告)日：2015-09-29

申请号：US12980878

申请日：2010-12-29

Applicant: Tapas Nandy ,  Nitin Gupta

Inventor： Tapas Nandy ,  Nitin Gupta

IPC: H03K17/16 ,  H03K19/003 ,  H03F3/45

CPC classification number: H03F3/45928 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2200/411 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45596 ,  H03F2203/45631 ,  H03F2203/45702

Abstract: An embodiment of a transmitter includes an amplifier having first and second differential output nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential output node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential output node and having a second node coupled to the supply node. An embodiment of a receiver includes an amplifier having first and second differential input nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential input node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential input node and having a second node coupled to the supply node. In an embodiment, the transmitter and receiver are capacitively coupled to one another.

Abstract translation: 发射机的实施例包括具有第一和第二差分输出节点的放大器，第一供电节点，第一上拉阻抗，其具有耦合到第一差分输出节点的第一节点并且具有耦合到供电节点的第二节点，以及 第二上拉阻抗，其具有耦合到所述第二差分输出节点并且具有耦合到所述电源节点的第二节点的第一节点。 接收机的实施例包括具有第一和第二差分输入节点的放大器，第一供电节点，第一上拉阻抗，其具有耦合到第一差分输入节点的第一节点并且具有耦合到供应节点的第二节点，以及 第二上拉阻抗，其具有耦合到所述第二差分输入节点并具有耦合到所述电源节点的第二节点的第一节点。 在一个实施例中，发射机和接收机彼此电容耦合。