公开(公告)号：US10211059B2

公开(公告)日：2019-02-19

申请号：US15601115

申请日：2017-05-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L29/49 ,  H01L21/28

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

公开(公告)号：US20180375428A1

公开(公告)日：2018-12-27

申请号：US16012410

申请日：2018-06-19

Applicant: STMicroelectronics SA

Inventor： Thierry Di Gilio

IPC: H02M3/07 ,  H02M1/36 ,  H03K17/30

Abstract: The disclosure relates to a negative charge pump circuit including a first capacitor; a first selector switch; a second selector switch; and a control circuit designed to, in a first phase of operation, alternately control the first and second selector switches in a first configuration in which the first and second electrodes of the first capacitor are respectively linked to the first and second nodes and in a second configuration in which the first and second electrodes of the first capacitor are respectively linked to the second and third nodes. In a second phase of operation, the control circuit forces the first selector switch to link the first electrode of the first capacitor to the second node and control the second selector switch so as to alternately link the second electrode of the first capacitor to the second and to the third node.

公开(公告)号：US20180351353A1

公开(公告)日：2018-12-06

申请号：US15607780

申请日：2017-05-30

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics SA

Inventor： Yves Mazoyer ,  Philippe Galy ,  Philippe Sirito-Olivier

IPC: H02H9/04 ,  H02H9/00 ,  H01L27/02 ,  H01L23/62 ,  H01L23/60

Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.

公开(公告)号：US10145870B2

公开(公告)日：2018-12-04

申请号：US15357244

申请日：2016-11-21

Applicant: STMicroelectronics SA

Inventor： Bruno Delplanque

IPC: G01R11/63 ,  G01R22/10 ,  G01R31/317 ,  G06F1/32 ,  H04L7/00 ,  G01R21/133

Abstract: A reference clock signal of at least one module clock signal associated with each module is delivered. A measurement period is generated and a module whose consumption is to be determined is selected. The frequency of the at least one module clock signal associated with the selected module reduced during the measurement period. A measurement of a first consumption of the device is made in the measurement period. A measurement of a second consumption of the device is made outside the measurement period. The consumption of the selected module is determined from the first and measured first and second consumptions.

公开(公告)号：US10135451B2

公开(公告)日：2018-11-20

申请号：US15800302

申请日：2017-11-01

Applicant: STMicroelectronics SA

Inventor： Marc Houdebine ,  Sebastien Dedieu

IPC: H03L7/197 ,  H04L7/033 ,  H03L7/089

Abstract: In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.

公开(公告)号：US20180323196A1

公开(公告)日：2018-11-08

申请号：US16038705

申请日：2018-07-18

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Florian Cacho ,  Vincent Huard

IPC: H01L27/092 ,  H03K19/21 ,  H03K19/094 ,  H03K19/003 ,  G01R31/317 ,  H01L29/10 ,  H03K3/037 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  G01R31/31725 ,  H01L21/823892 ,  H01L29/1083 ,  H03K3/037 ,  H03K19/00315 ,  H03K19/094 ,  H03K19/21

Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.

公开(公告)号：US20180276536A1

公开(公告)日：2018-09-27

申请号：US15697598

申请日：2017-09-07

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54

CPC classification number: G06N3/063 ,  G06N3/049 ,  G06N3/0635 ,  G11C11/54

Abstract: An integrated artificial neuron device includes a refractory circuit configured to inhibit signal integration for an inhibition duration after delivery of an output signal. The refractory circuit includes a first MOS transistor coupled between an input node and a reference node and having a gate connected to the output node by a second MOS transistor having a first electrode coupled to the supply node and a gate coupled to the output node. The refractory circuit further includes a resistive-capacitive circuit coupled between the supply node, the reference node and the gate of the second MOS transistor. An inhibition duration depends on a time constant of the resistive-capacitive circuit.

公开(公告)号：US20180269886A1

公开(公告)日：2018-09-20

申请号：US15800302

申请日：2017-11-01

Applicant: STMicroelectronics SA

Inventor： Marc Houdebine ,  Sebastien Dedieu

IPC: H03L7/197 ,  H03L7/089 ,  H04L7/033

CPC classification number: H03L7/1974 ,  H03K5/00006 ,  H03L7/0891 ,  H03L7/1976 ,  H03L2207/10 ,  H04L7/0331

Abstract: In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.

公开(公告)号：US20180254753A1

公开(公告)日：2018-09-06

申请号：US15683236

申请日：2017-08-22

Applicant: STMicroelectronics SA

Inventor： Jean-Pierre Blanc ,  Severin Trochut

IPC: H03F1/30 ,  H03F1/02 ,  H03F3/04

CPC classification number: H03F1/302 ,  G05F3/30 ,  H03F1/0205 ,  H03F3/04 ,  H03F2200/447

Abstract: A voltage or current generator has a configurable temperature coefficient and includes a first voltage generator that generates a first voltage having a first negative temperature coefficient. A second voltage generator generates a second voltage having a second negative temperature coefficient different to the first negative temperature coefficient. A circuit generates an output level based on the difference between the first voltage scaled by a first scale factor and the second voltage scaled by a second scale factor.

公开(公告)号：US09998178B2

公开(公告)日：2018-06-12

申请号：US15436826

申请日：2017-02-19

Applicant: STMicroelectronics SA

Inventor： Sebastien Dedieu ,  Marc Houdebine

IPC: H04B5/00 ,  H03L7/099 ,  H03L7/093 ,  H03L7/081 ,  G06K7/10

CPC classification number: H04B5/0031 ,  G06K7/10297 ,  H03L7/08 ,  H03L7/081 ,  H03L7/093 ,  H03L7/099 ,  H03L7/14 ,  H03L7/23 ,  H04B5/0056 ,  H04B5/0062 ,  H04B5/0093 ,  H04W4/80

Abstract: A method can be used for contactless communication of an object with a reader using active load modulation. A main clock signal is generated within the object. The generating includes a calibration phase and a transmission phase. The calibration phase includes locking an output signal of a controlled main oscillator onto a phase and frequency of a secondary clock signal received from the reader and estimating a frequency ratio between a frequency of the output signal of the main oscillator and a reference frequency of a reference signal originating from a reference oscillator. The transmission phase includes only frequency-locking the output signal of the main oscillator onto the frequency of the reference signal corrected by the estimated frequency ratio.