公开(公告)号：US06931295B2

公开(公告)日：2005-08-16

申请号：US10725239

申请日：2003-12-01

Applicant: Chun-Hung Lin ,  Ta-Chin Lin

Inventor： Chun-Hung Lin ,  Ta-Chin Lin

IPC: G06F19/00 ,  G06Q10/00

CPC classification number: G06Q10/06

Abstract: A method of calculating lot hold time. First, identification parameters of a lot are input. The lot may be a split child lot or an unsplit parent lot. The identification parameters include an identification code and a customer hold code of the lot. The identification code identifies the lot type. The customer hold code identifies the holder. Lot hold time is then calculated according to the identification parameters. Finally, the lot hold time is output for further utilization.

Abstract translation: 计算批次持续时间的方法。 首先，输入很多的识别参数。 这个地段可能是一个分裂的小孩，也可能是一个非分裂的父母。 识别参数包括批次的识别码和客户保留码。 识别码识别批次类型。 客户保留代码标识持有人。 然后根据识别参数计算批次保持时间。 最后，批次保留时间输出以供进一步利用。

公开(公告)号：US20050119775A1

公开(公告)日：2005-06-02

申请号：US10725239

申请日：2003-12-01

Applicant: Chun-Hung Lin ,  Ta-Chin Lin

Inventor： Chun-Hung Lin ,  Ta-Chin Lin

IPC: G06F19/00 ,  G06Q10/00

CPC classification number: G06Q10/06

Abstract: A method of calculating lot hold time. First, identification parameters of a lot are input. The lot may be a split child lot or an unsplit parent lot. The identification parameters include an identification code and a customer hold code of the lot. The identification code identifies the lot type. The customer hold code identifies the holder. Lot hold time is then calculated according to the identification parameters. Finally, the lot hold time is output for further utilization.

Abstract translation: 计算批次持续时间的方法。 首先，输入很多的识别参数。 这个地段可能是一个分裂的小孩，也可能是一个非分裂的父母。 识别参数包括批次的识别码和客户保持码。 识别码识别批次类型。 客户保留代码标识持有人。 然后根据识别参数计算批次保持时间。 最后，批次保留时间输出以供进一步利用。

公开(公告)号：US06793337B1

公开(公告)日：2004-09-21

申请号：US10701445

申请日：2003-11-06

Applicant: Chun-Hung Lin

Inventor： Chun-Hung Lin

IPC: G02C100

CPC classification number: G02C5/12

Abstract: A nose pad of eyeglasses includes a nose rack, a fastener and a pad; an axis is on the nose rack, a sleeve corresponding to the axis is on the fastener, an insertion hole is on the sleeve for the axis to insert. The open of the insertion hole is smaller than the diameter of the axis, users can install and remove them easily, and avoid scratches and breakage during installation and removal.

Abstract translation: 眼镜鼻垫包括鼻架，紧固件和衬垫; 一个轴线在鼻架上，一个对应于该轴线的套筒在紧固件上，一个插入孔位于套筒上用于轴线插入。 插入孔的开口小于轴的直径，用户可以轻松安装和拆卸，避免在安装和拆卸过程中划伤和破损。

公开(公告)号：US06789079B2

公开(公告)日：2004-09-07

申请号：US09971842

申请日：2001-10-05

Applicant: Da-Yi Chang ,  Chun-Hung Lin ,  Kun-Pei Li ,  Hsiu-Lan Ting ,  Kung-Cheng Tu ,  Mao-Shing Sun

Inventor： Da-Yi Chang ,  Chun-Hung Lin ,  Kun-Pei Li ,  Hsiu-Lan Ting ,  Kung-Cheng Tu ,  Mao-Shing Sun

IPC: G06F1730

CPC classification number: G06F17/30873 ,  Y10S707/99933

Abstract: The present invention discloses an integrated service platform (ISP). Under the real-time mode, the ISP of the present invention comprises the devices of: an engineering data analysis database (EDB); an area controller database (AC Database); a web server; and client computers. Under the mode of accessing data in a certain period of time, the present invention comprises the devices of: an EDB; an AC Database; a loader; a web server; and client computers. The application of the ISP of the present invention allows users on the client sites to access the data they want with browsers. Thus, no disturbance of the maintenance on the client sites would occur, because the browsers are used for accessing the data.

Abstract translation: 本发明公开了一种综合业务平台（ISP）。 在实时模式下，本发明的ISP包括：工程数据分析数据库（EDB）; 区域控制器数据库（AC数据库）; 网络服务器 和客户端计算机。 在一段时间内访问数据的模式下，本发明包括以下设备：EDB; AC数据库 装载机 网络服务器 和客户端计算机。 本发明的ISP的应用允许客户端站点上的用户使用浏览器访问他们想要的数据。 因此，由于浏览器用于访问数据，因此不会对客户端站点的维护造成干扰。

公开(公告)号：US06718430B2

公开(公告)日：2004-04-06

申请号：US09990392

申请日：2001-11-20

Applicant: Chun-Hung Lin ,  Chih-Hung Wang ,  Chun-Hao Kuo

Inventor： Chun-Hung Lin ,  Chih-Hung Wang ,  Chun-Hao Kuo

IPC: G06F1200

CPC classification number: G06F12/0246 ,  G06F11/1068 ,  G06F11/1435 ,  G06F12/0292 ,  G06F2212/7203

Abstract: A window-based flash memory storage system and a management and an access method therefor are proposed. The window-based flash memory storage system includes a window-based region and a redundant reserved region; wherein the window-based region is used to store a number of windows, each window being associated with a number of physical blocks. The redundant reserved region includes a dynamic-link area, a window-information area, a dynamic-link information area, and an boot-information area; wherein the dynamic-link area includes a plurality of dynamic allocation blocks, each being allocatable to any window. The window-information area is used to store a specific window-information set that is dedicated to a certain window within a specific range of data storage space. The dynamic-link information area is used to record the status of the allocation of the dynamic allocation blocks to the windows.

公开(公告)号：US06660138B2

公开(公告)日：2003-12-09

申请号：US10076289

申请日：2002-02-19

Applicant: Chun-Hung Lin ,  Chen-Der Tsai ,  Yun-Sheng Chung ,  Chin-Ching Wu ,  Yuh-Feng Chen ,  Hann-Tsong Wang

Inventor： Chun-Hung Lin ,  Chen-Der Tsai ,  Yun-Sheng Chung ,  Chin-Ching Wu ,  Yuh-Feng Chen ,  Hann-Tsong Wang

IPC: B23H1100

CPC classification number: C25F3/16 ,  C25F7/00

Abstract: The present invention is an electropolishing process and device for electropolishing an inner surface of a long tube, especially applied to a long tube of greater than two meters and a diameter range between 0.3 and 5 cm. Wherein, the present invention comprises at least one tube, and one complex electrode. An inner surface of the tube is for electropolishing process, and it is an anode as well. The electrode is a cathode and placed on a center of a partition. An end of electrode connects to a cable, the cable is driven by an axial mechanism to be moved the electrode toward the axial mechanism itself. Inside of the tube is full o electrolyte, which is an electrifying medium to connect both anode and cathode. Further, electrolyte cooperates with the electrode to perform the electropolishing process on the inner surface of tube.

Abstract translation: 本发明是用于电解抛光长管的内表面的电抛光方法和装置，特别是应用于大于2米的长管和0.3和5cm之间的直径范围。 其中，本发明包括至少一个管和一个复合电极。 管的内表面用于电解抛光工艺，它也是阳极。 电极是阴极并放置在隔板的中心。 电极的一端连接到电缆，电缆由轴向机构驱动，以将电极移向轴向机构本身。 管内是全o电解质，它是连接阳极和阴极的通电介质。 此外，电解质与电极配合以在管的内表面上进行电解抛光处理。

公开(公告)号：US06573123B2

公开(公告)日：2003-06-03

申请号：US10029845

申请日：2001-12-31

Applicant: Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

Inventor： Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

公开(公告)号：US06348399B1

公开(公告)日：2002-02-19

申请号：US09610857

申请日：2000-07-06

Applicant: Chun Hung Lin

Inventor： Chun Hung Lin

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/566 ,  H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05171

Abstract: A method of making a chip scale package comprises the following steps: providing a semiconductor chip having a plurality of metal bumps formed on the active surface thereof; providing a metal plate having a plurality of flip-chip pads formed on a surface thereof; positioning the semiconductor chip on the surface of the metal plate with the metal bumps on the chip aligned with the flip-chip pads on the metal plate; connecting the metal bumps on the active surface of the semiconductor chip to the flip-chip pads on the surface of the metal plate; encapsulating the semiconductor chip against a portion of the surface of the metal plate; removing the metal plate while leaving the flip-chip pads intact; and forming a plurality of solder balls on the flip-chip pads. Using the technique of the present invention, it becomes possible that the manufacture of a molded chip scale package can be relatively simplified and economical, yet highly reliable.

Abstract translation: 制造芯片级封装的方法包括以下步骤：提供在其有效表面上形成有多个金属凸块的半导体芯片; 提供具有形成在其表面上的多个倒装芯片焊盘的金属板; 将半导体芯片定位在金属板的表面上，其中芯片上的金属凸块与金属板上的倒装芯片对准; 将半导体芯片的有源表面上的金属凸块连接到金属板表面上的倒装芯片焊盘; 将半导体芯片封装在金属板表面的一部分上; 去除金属板，同时使倒装芯片垫完好无损; 以及在所述倒装芯片焊盘上形成多个焊球。 使用本发明的技术，可以相对简单且经济地而且高度可靠地制造模制芯片级封装。

公开(公告)号：US06333562B1

公开(公告)日：2001-12-25

申请号：US09615836

申请日：2000-07-13

Applicant: Chun Hung Lin

Inventor： Chun Hung Lin

IPC: H01L2940

CPC classification number: H01L24/85 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/83136 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/85186 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: A multichip module mainly comprises two stacked chips disposed on and respectively wire bonded to a substrate or a lead frame. There are a plurality of electrically conductive bumps having base portions and pillar protruding portions interposed between the two chips. The conductive bumps are attached at their base portions to the bonding pads of the lower chip and connected at their pillar protruding portions to the backside surface of the upper chip so as to support the upper chip. In the multichip module of the present invention, the pillar protruding portions of bumps help to provide clearance between the two chips for keeping the upper chip from damaging the bonding wires of the lower chip.

Abstract translation: 多芯片模块主要包括两个堆叠的芯片，其布置在引线框架上并分别引线接合到基板或引线框架上。 存在多个导电凸块，其具有插入在两个芯片之间的基部和柱突出部。 导电凸块在其底部附着到下芯片的接合焊盘，并在其突出部分连接到上芯片的背面，以支撑上芯片。 在本发明的多芯片模块中，凸块的支柱突出部有助于在两个芯片之间提供间隙，以保持上部芯片不会损坏下部芯片的接合线。

公开(公告)号：US5919673A

公开(公告)日：1999-07-06

申请号：US408774

申请日：1995-03-22

Applicant: Chi-Huey Wong ,  Chun-Hung Lin ,  Gwo-Jenn Shen

Inventor： Chi-Huey Wong ,  Chun-Hung Lin ,  Gwo-Jenn Shen

IPC: C12N9/10 ,  C12N9/12 ,  C12P11/00 ,  C12P19/26 ,  C12P19/30 ,  C12P19/04 ,  C12P19/32 ,  C12P33/00

CPC classification number: C12N9/13 ,  C12N9/1205 ,  C12N9/1241 ,  C12P11/00 ,  C12P19/26 ,  C12P19/30

Abstract: A process for the enzymatic synthase of sulfate esters is disclosed in which intermediate phosphorylated adenosine compounds are recycled to minimize enzyme inhibition. Exemplary enzymes include ATP sulfurylase, APS kinase and a sulfotransferase.

Abstract translation: 公开了一种硫酸酯酶合成酶的方法，其中中间磷酸化腺苷化合物被循环以使酶抑制最小化。 示例性的酶包括ATP硫酸化酶，APS激酶和磺基转移酶。