-
公开(公告)号:US20240234448A1
公开(公告)日:2024-07-11
申请号:US18151509
申请日:2023-01-09
Applicant: GlobalFoundries U.S. Inc.
Inventor: DAVID PRITCHARD , HONG YU , ZHIXING ZHAO
IPC: H01L27/13 , H01L21/762 , H01L21/84 , H01L27/12
CPC classification number: H01L27/13 , H01L21/76283 , H01L21/84 , H01L27/1203
Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate electrode, an isolation structure, and an electrode plate. The gate electrode is over the substrate and the isolation structure is in contact with the gate electrode. The electrode plate is in the isolation structure.
-
公开(公告)号:US20240234346A1
公开(公告)日:2024-07-11
申请号:US18095156
申请日:2023-01-10
Applicant: GlobalFoundries U.S. Inc.
Inventor: Mark D. LEVY , Brett T. CUCCI , Spencer H. PORTER , Santosh SHARMA
IPC: H01L23/58 , H01L23/31 , H01L23/532 , H01L29/06 , H01L29/66 , H01L29/778
CPC classification number: H01L23/585 , H01L23/3178 , H01L23/53295 , H01L29/0657 , H01L29/66462 , H01L29/7786 , H01L23/291
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to seal ring structures and methods of manufacture. The structure includes: a semiconductor substrate; a channel layer above the semiconductor substrate; a trench within the channel layer, extending to the semiconductor substrate; and a moisture barrier layer lining sidewalls and a bottom surface of the trench.
-
公开(公告)号:US12034039B2
公开(公告)日:2024-07-09
申请号:US17451172
申请日:2021-10-18
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor: EeJan Khor , Ramasamy Chockalingam , Juan Boon Tan
IPC: H01L49/02
CPC classification number: H01L28/92
Abstract: A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.
-
74.
公开(公告)号:US20240221810A1
公开(公告)日:2024-07-04
申请号:US18607725
申请日:2024-03-18
Applicant: GlobalFoundries U.S. Inc.
Inventor: Venkatesh P. Gopinath , Pirooz Parvarandeh
IPC: G11C11/22
CPC classification number: G11C11/223 , G11C11/2273 , G11C11/2275
Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.
-
公开(公告)号:US12027553B2
公开(公告)日:2024-07-02
申请号:US17896401
申请日:2022-08-26
Applicant: GlobalFoundries U.S. Inc.
Inventor: Siva P. Adusumilli , Vibhor Jain , Alvin J. Joseph , Steven M. Shank
IPC: H01L27/146
CPC classification number: H01L27/14629 , H01L27/1462 , H01L27/1463 , H01L27/14685
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.
-
76.
公开(公告)号:US20240210621A1
公开(公告)日:2024-06-27
申请号:US18597173
申请日:2024-03-06
Applicant: GlobalFoundries U.S. Inc.
Inventor: Brett T. Cucci , Yusheng Bian , Abdelsalam Aboketaf , Edward W. Kiewra
CPC classification number: G02B6/1228 , G02B6/1223 , G02B6/125 , G02B6/132 , G02B2006/12061 , G02B2006/12147 , G02B6/1225
Abstract: Disclosed are embodiments of a photonic integrated circuit (PIC) structure with a waveguide core having tapered sidewall liner(s) (e.g., symmetric tapered sidewall liners on opposing sides of a waveguide core, asymmetric tapered sidewall liners on opposing sides of a waveguide core, or a tapered sidewall liner on one side of a waveguide core). In some embodiments, the tapered sidewall liner(s) and waveguide core have different refractive indices. In an exemplary embodiment, the waveguide core is a first material (e.g., silicon) and the tapered sidewall liner(s) is/are a second material (e.g., silicon nitride) with a smaller refractive index than the first material. In another exemplary embodiment, the waveguide core is a first compound and the tapered sidewall liner(s) is/are a second compound with the same elements (e.g., silicon and nitrogen) as the first compound but with a smaller refractive index. Also disclosed are method embodiments for forming such a PIC structure.
-
公开(公告)号:US20240201438A1
公开(公告)日:2024-06-20
申请号:US18084921
申请日:2022-12-20
Applicant: GlobalFoundries U.S. Inc.
Inventor: Yusheng Bian
IPC: G02B6/122 , G02B6/13 , H01L31/0232 , H01L31/028 , H01L31/105 , H01L31/18
CPC classification number: G02B6/1228 , G02B6/13 , H01L31/02327 , H01L31/028 , H01L31/105 , H01L31/1808
Abstract: Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a photodetector including a pad having a side edge and a light-absorbing layer disposed on the pad. The structure further comprises a waveguide core including a tapered section positioned adjacent to the side edge of the pad and the light-absorbing layer. The tapered section has a width dimension that decreases with decreasing distance from the side edge of the pad.
-
78.
公开(公告)号:US20240195416A1
公开(公告)日:2024-06-13
申请号:US18064978
申请日:2022-12-13
Applicant: GlobalFoundries U.S. Inc.
Inventor: Dzung T. Tran , Deepti A. Pant , Shibly S. Ahmed
IPC: H03K19/003
CPC classification number: H03K19/00361 , H03K19/00315
Abstract: Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.
-
公开(公告)号:US20240194714A1
公开(公告)日:2024-06-13
申请号:US18064890
申请日:2022-12-12
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor: Ping ZHENG , Eng Huat TOH , Cancan WU , Kiok Boone Elgin QUEK
IPC: H01L27/146
CPC classification number: H01L27/1463 , H01L27/1462 , H01L27/14627 , H01L27/14683
Abstract: A photodiode device includes a semiconductor substrate, a plurality of pixels, each of the pixels including a diode structure on a first side of the substrate and a conductive layer on a second side of the substrate, and DTI structures isolating adjacent pixels from one another, the DTI structures including a conductive material that electrically couples the conductive layer on the second side of the substrate and a metal line on the first side of the substrate. The conductive material in the DTI structures is part of an electrode circuit for the pixels.
-
公开(公告)号:US20240194667A1
公开(公告)日:2024-06-13
申请号:US18077299
申请日:2022-12-08
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor: Kyongjin Hwang , Robert Gauthier, JR.
IPC: H01L27/02
CPC classification number: H01L27/0259
Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including first and second trench isolation regions positioned in the semiconductor substrate. The first trench isolation region extends to a first depth in the semiconductor substrate, and the second trench isolation region extends to a second depth in the semiconductor substrate. The second depth is greater than the first depth. A bipolar junction transistor structure includes a collector, an emitter, and a base each disposed in the semiconductor substrate. The collector includes a portion that extends to the top surface of the semiconductor substrate, the first trench isolation region is positioned in the base, the second trench isolation region is positioned in a lateral direction between the portion of the collector and the base, and the second trench isolation region surrounds the base, the emitter, and the first trench isolation region.
-
-
-
-
-
-
-
-
-