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    Three electrode capacitor structure using spaced conductive pillars
    73.
    发明授权
    Three electrode capacitor structure using spaced conductive pillars 有权

    公开(公告)号：US12034039B2

    公开(公告)日：2024-07-09

    申请号：US17451172

    申请日：2021-10-18

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： EeJan Khor ,  Ramasamy Chockalingam ,  Juan Boon Tan

    IPC: H01L49/02

    CPC classification number: H01L28/92

    Abstract: A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.

    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS
    74.
    发明公开
    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS 审中-公开

    公开(公告)号：US20240221810A1

    公开(公告)日：2024-07-04

    申请号：US18607725

    申请日：2024-03-18

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC: G11C11/22

    CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C11/2275

    Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER
    78.
    发明公开
    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER 审中-公开

    公开(公告)号：US20240195416A1

    公开(公告)日：2024-06-13

    申请号：US18064978

    申请日：2022-12-13

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Dzung T. Tran ,  Deepti A. Pant ,  Shibly S. Ahmed

    IPC: H03K19/003

    CPC classification number: H03K19/00361 ,  H03K19/00315

    Abstract: Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.

    ELECTROSTATIC DISCHARGE PROTECTION DEVICES WITH MULTIPLE-DEPTH TRENCH ISOLATION
    80.
    发明公开
    ELECTROSTATIC DISCHARGE PROTECTION DEVICES WITH MULTIPLE-DEPTH TRENCH ISOLATION 审中-公开

    公开(公告)号：US20240194667A1

    公开(公告)日：2024-06-13

    申请号：US18077299

    申请日：2022-12-08

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Kyongjin Hwang ,  Robert Gauthier, JR.

    IPC: H01L27/02

    CPC classification number: H01L27/0259

    Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including first and second trench isolation regions positioned in the semiconductor substrate. The first trench isolation region extends to a first depth in the semiconductor substrate, and the second trench isolation region extends to a second depth in the semiconductor substrate. The second depth is greater than the first depth. A bipolar junction transistor structure includes a collector, an emitter, and a base each disposed in the semiconductor substrate. The collector includes a portion that extends to the top surface of the semiconductor substrate, the first trench isolation region is positioned in the base, the second trench isolation region is positioned in a lateral direction between the portion of the collector and the base, and the second trench isolation region surrounds the base, the emitter, and the first trench isolation region.

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