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    Nonvolatile Memory Devices that Use Resistance Materials and Internal Electrodes, and Related Methods and Processing Systems
    71.
    发明申请
    Nonvolatile Memory Devices that Use Resistance Materials and Internal Electrodes, and Related Methods and Processing Systems 有权
    使用电阻材料和内部电极的非易失性存储器件，以及相关方法和处理系统

    公开(公告)号：US20090230512A1

    公开(公告)日：2009-09-17

    申请号：US12353553

    申请日：2009-01-14

    Applicant: In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

    Inventor： In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

    IPC: H01L29/00

    CPC classification number: G11C13/0007 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

    Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

    Abstract translation: 非易失性存储器件，非易失性存储器件的制造方法和包括非易失性存储器件的处理系统。 非易失性存储装置可以包括沿基板垂直于基板的方向延伸的多个内部电极，基本上平行于基板的表面延伸的多个第一外部电极和多个第二外部电极 其也基本上平行于衬底的表面延伸。 每个第一外部电极在相应的一个内部电极的第一侧上，并且每个第二外部电极在相应的一个内部电极的第二侧上。 这些器件还包括接触内部电极，第一外部电极和第二外部电极的多个可变电阻器。

    METHODS OF PROGRAMMING NON-VOLATILE MEMORY DEVICES INCLUDING TRANSITION METAL OXIDE LAYER AS DATA STORAGE MATERIAL LAYER AND DEVICES SO OPERATED
    75.
    发明申请
    METHODS OF PROGRAMMING NON-VOLATILE MEMORY DEVICES INCLUDING TRANSITION METAL OXIDE LAYER AS DATA STORAGE MATERIAL LAYER AND DEVICES SO OPERATED 有权
    编写非易失性存储器件的方法，包括过渡金属氧化物层作为数据存储材料层和操作的器件

    公开(公告)号：US20070228370A1

    公开(公告)日：2007-10-04

    申请号：US11762483

    申请日：2007-06-13

    Applicant: Moon-Sook Lee ,  In-Gyu Baek

    Inventor： Moon-Sook Lee ,  In-Gyu Baek

    IPC: G11C11/00 ,  H01L29/12

    CPC classification number: G11C13/00 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

    Abstract: A method of programming a non-volatile memory device including a transition metal oxide layer includes applying a first electric pulse to the transition metal oxide layer for a first period to establish a resistance of the transition metal oxide layer and applying a second electric pulse to the transition metal oxide layer for a second period, longer than the first period, to increase the resistance of the transition metal oxide layer. Related devices are also disclosed.

    Abstract translation: 一种对包括过渡金属氧化物层的非易失性存储器件进行编程的方法包括：将第一电脉冲施加到过渡金属氧化物层第一周期以建立过渡金属氧化物层的电阻并向第二电脉冲施加第二电脉冲 过渡金属氧化物层，延长第一周期，以增加过渡金属氧化物层的电阻。 还公开了相关设备。

    Resistive memory cells and devices having asymmetrical contacts
    77.
    发明授权
    Resistive memory cells and devices having asymmetrical contacts 有权
    具有不对称触点的电阻式存储单元和器件

    公开(公告)号：US08873274B2

    公开(公告)日：2014-10-28

    申请号：US13862918

    申请日：2013-04-15

    Applicant: In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

    Inventor： In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

    IPC: G11C11/00

    CPC classification number: H01L45/04 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

    Abstract translation: 存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。 第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。 例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。 磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

    Non-volatile memory devices having resistance changeable elements and related systems and methods
    79.
    发明授权
    Non-volatile memory devices having resistance changeable elements and related systems and methods 有权
    具有电阻变化元件和相关系统和方法的非易失性存储器件

    公开(公告)号：US08664633B2

    公开(公告)日：2014-03-04

    申请号：US13220777

    申请日：2011-08-30

    Applicant: Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

    Inventor： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

    IPC: H01L29/06

    CPC classification number: H01L27/1021 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

    Abstract: A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

    Abstract translation: 非易失性存储器件可以包括衬底上的第一字线，第一字线上的绝缘层和绝缘层上的第二字线，使得绝缘层在第一和第二字线之间。 位柱可以在相对于衬底的表面垂直的方向上相邻于第一字线，绝缘层和第二字线延伸，并且位柱可以是导电的。 此外，第一存储单元可以包括电耦合在第一字线和位柱之间的第一电阻可变元件，并且第二存储单元可以包括电耦合在第二字线和位柱之间的第二电阻可变元件。 还讨论了相关方法和系统。

    Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same
    80.
    发明授权
    Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same 有权
    具有堆叠结构的半导体存储器件，包括基于电阻开关的逻辑电路及其制造方法

    公开(公告)号：US08553445B2

    公开(公告)日：2013-10-08

    申请号：US13224410

    申请日：2011-09-02

    Applicant: In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

    Inventor： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

    IPC: G11C11/00

    CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

    Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

    Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

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