公开(公告)号：US08377817B2

公开(公告)日：2013-02-19

申请号：US13173304

申请日：2011-06-30

申请人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

发明人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC分类号： H01L21/4763

CPC分类号： H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

公开(公告)号：US20130005104A1

公开(公告)日：2013-01-03

申请号：US13615890

申请日：2012-09-14

申请人： ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

发明人： ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926

摘要： Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括堆叠结构，半导体图案，信息存储层和固定电荷层。 堆叠结构可以设置在半导体衬底上。 层叠结构可以包括交替堆叠在其中的导电图案和层间电介质图案。 半导体图案可以通过层叠结构连接到半导体衬底。 信息存储层可以设置在半导体图案和导电图案之间。 固定电荷层可以设置在半导体图案和层间电介质图案之间。 固定电荷层可以包括固定电荷。 固定电荷的电极性可以等于半导体图案的多数载流子的电极性。

公开(公告)号：US20120248525A1

公开(公告)日：2012-10-04

申请号：US13401013

申请日：2012-02-21

申请人： Sunghae LEE ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

发明人： Sunghae LEE ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L27/11582 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7827

摘要： Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

摘要翻译： 提供三维半导体存储器件及其制造方法。 根据该方法，将牺牲层和绝缘层交替重复堆叠在基板上，并且形成贯穿牺牲层的最上层牺牲层的切割区域。 切割区域填充有非牺牲层。 将绝缘层和牺牲层图案化以形成模具图案。 模具图案包括切割区域中的绝缘图案，牺牲图案和非牺牲层。 牺牲图案可以用电极代替。 还提供了相关的半导体存储器件。

公开(公告)号：US20120104485A1

公开(公告)日：2012-05-03

申请号：US13281784

申请日：2011-10-26

申请人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

发明人： Junkyu Yang ,  HongSuk Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  Guk-Hyon Yon

IPC分类号： H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/764 ,  H01L27/11568

摘要： A method of manufacturing a nonvolatile memory device includes forming a tunnel dielectric layer, a charge storage layer, and a hard mask layer on a substrate in sequential order. Active portions are defined by forming trenches in the substrate. A tunnel dielectric pattern, a preliminary charge storage pattern, and a hard mask pattern are formed on each of the active portions in sequential order by sequentially patterning the hard mask layer, the charge storage layer, the tunnel dielectric layer, and the substrate. A capping pattern is formed covering an upper surface of the trenches such that a first void remains in a lower portion of the trenches, the capping pattern including etch particles formed by etching the hard mask pattern through a sputtering etch process.

摘要翻译： 一种制造非易失性存储器件的方法包括在衬底上依次形成隧道介电层，电荷存储层和硬掩模层。 通过在衬底中形成沟槽来限定活性部分。 通过对硬掩模层，电荷存储层，隧道介电层和衬底进行顺序构图，按顺序在有源部分的每一个上形成隧道电介质图案，初电电荷存储图案和硬掩模图案。 形成覆盖沟槽的上表面的覆盖图案，使得第一空隙保留在沟槽的下部，封盖图案包括通过溅射蚀刻工艺蚀刻硬掩模图案形成的蚀刻颗粒。

公开(公告)号：US20110298038A1

公开(公告)日：2011-12-08

申请号：US13153009

申请日：2011-06-03

申请人： Yong-Hoon SON ,  Kihyun Hwang

发明人： Yong-Hoon SON ,  Kihyun Hwang

IPC分类号： H01L29/792

CPC分类号： H01L29/7889 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided are a three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device may include a gate structure on a substrate with the gate structure including a plurality of gate electrodes. Conductive lines are disposed between the gate structure and the substrate. A horizontal semiconductor pattern is disposed between the gate structure and the conductive line. And a vertical semiconductor pattern penetrating the gate structure is connected to the horizontal semiconductor pattern.

摘要翻译： 提供三维半导体存储器件和三维半导体存储器件的制造方法。 所述三维半导体存储器件可以包括栅极结构，所述栅极结构在所述栅极结构包括多个栅电极的基板上。 导电线设置在栅极结构和衬底之间。 在栅极结构和导电线之间设置水平半导体图案。 并且穿过栅极结构的垂直半导体图案连接到水平半导体图案。

公开(公告)号：US20110248327A1

公开(公告)日：2011-10-13

申请号：US13039043

申请日：2011-03-02

申请人： Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang ,  Seungjae Baik ,  Jung Ho Kim

发明人： Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang ,  Seungjae Baik ,  Jung Ho Kim

IPC分类号： H01L27/115

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.

摘要翻译： 非易失性存储器件包括在衬底上的一串非易失性存储器单元。 这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。 第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。 非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。 在衬底中提供连接掺杂半导体区域。 该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

公开(公告)号：US20110143524A1

公开(公告)日：2011-06-16

申请号：US12968595

申请日：2010-12-15

申请人： Yong-Hoon Son ,  Kihyun Hwang ,  Seungjae Baik

发明人： Yong-Hoon Son ,  Kihyun Hwang ,  Seungjae Baik

IPC分类号： H01L21/28 ,  H01L21/20

CPC分类号： H01L21/28 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

摘要： Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.

摘要翻译： 形成非易失性存储器件的方法包括在衬底上形成垂直堆叠的非易失性存储单元。 这通过在垂直硅有源层的第一侧壁上形成间隔开的栅电极的垂直堆叠来完成，并且处理垂直硅有源层的第二侧壁以便减少有源层内的晶体缺陷和/或减少界面 其中的陷阱密度。 该处理可以包括用氧化物质暴露第二侧壁，该氧化物质将第二侧壁的表面转化为二氧化硅钝化层。 也可以直接在二氧化硅钝化层上形成掩埋绝缘图案。

公开(公告)号：US20100048012A1

公开(公告)日：2010-02-25

申请号：US12461188

申请日：2009-08-04

申请人： Juyul Lee ,  Seungjae Baik ,  Kihyun Hwang ,  Siyoung Choi

发明人： Juyul Lee ,  Seungjae Baik ,  Kihyun Hwang ,  Siyoung Choi

IPC分类号： H01L21/8246 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/11565 ,  H01L27/11573

摘要： Provided is a method for fabricating a nonvolatile memory device capable of improving charge retention characteristics. The method for fabricating a nonvolatile memory device includes forming a charge trapping layer with a memory region and a charge blocking region on a semiconductor substrate, and trapping charges in the charge blocking region of the charge trapping layer.

摘要翻译： 提供一种制造能够改善电荷保持特性的非易失性存储器件的方法。 非易失性存储器件的制造方法包括在半导体衬底上形成具有存储区域和电荷阻挡区域的电荷俘获层，并且在电荷俘获层的电荷阻挡区域中俘获电荷。