公开(公告)号：US20240394062A1

公开(公告)日：2024-11-28

申请号：US18534203

申请日：2023-12-08

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F9/38 ,  G06F9/30

Abstract: In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.

公开(公告)号：US12088285B2

公开(公告)日：2024-09-10

申请号：US17548988

申请日：2021-12-13

Applicant: Microchip Technology Inc.

Inventor： Tamir Langer ,  Migel Jacubovski

IPC: H03K17/082 ,  G01K7/01 ,  H02H5/04 ,  H03K17/08

CPC classification number: H03K17/0822 ,  G01K7/01 ,  H02H5/044 ,  H03K2017/0806

Abstract: A method provides thermal protection for an IC device that has multiple components. For each component, temperatures are sensed, each of which associated with a different area of the respective component and a respective temperature sense signal is output indicative of the highest sensed temperature of the respective component. For each of the components, the respective temperature sense output signal is sampled to produce a sequence of discrete sampled temperature values. A sequence of differences between a reference temperature value and each of the discrete sample temperatures is integrated over time to compute, for each of the components, a respective integration output. The respective integration output computed for each of the switches is compared to a threshold value. An action related to the thermal protection function is initiated upon the integration output of an affected component exceeding the threshold value.

公开(公告)号：US11934696B2

公开(公告)日：2024-03-19

申请号：US17398091

申请日：2021-08-10

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G06N3/08

Abstract: A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.

公开(公告)号：US11916662B2

公开(公告)日：2024-02-27

申请号：US17745060

申请日：2022-05-16

Applicant: Microchip Technology Inc.

Inventor： Steven Scott Gorshe ,  Winston Mok

IPC: H04B10/00 ,  H04J3/16 ,  H04J3/07 ,  H04J3/12 ,  H04J14/00

CPC classification number: H04J3/1658 ,  H04J3/07 ,  H04J3/12 ,  H04J2203/0085

Abstract: A system and method for performing rate adaptation of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of pseudo-Ethernet packets at a source node, assembling a plurality of Generic Mapping Procedure (GMP) frames by mapping a plurality of blocks from a stream of encoded blocks of CBR client data, a plurality of pad blocks, and GMP overhead into consecutive pseudo-Ethernet packets of the plurality of pseudo-Ethernet packets, inserting a fixed number of idle blocks between one or more of the consecutive pseudo-Ethernet packets and inserting an MTN path overhead (POH) frame that is aligned to the plurality of GMP frames to generate a plurality of rate adapted GMP frames for transmission over the MTN to an intermediate node or a sink node.

公开(公告)号：US11699493B2

公开(公告)日：2023-07-11

申请号：US17385857

申请日：2021-07-26

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G11C16/34 ,  G06N3/08 ,  G11C16/26 ,  G06N3/063 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G06N3/063 ,  G06N3/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3495

Abstract: A method for performing a read of a flash memory includes storing configuration files for a plurality of RRD-compensating RNNs. A current number of PE cycles for a flash memory are identified and TVSO values are identified corresponding to the current number of PE cycles. A current retention time and a current number of read disturbs for the flash memory are identified. The configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and current number of read disturbs is selected and is loaded into a neural network engine to form an RNN core in the neural network engine. A neural network operation of the RNN core is performed to predict RRD-compensated TVSO values. The input to the neural network operation includes the identified TVSO values. A read of the flash memory is performed using the predicted RRD-compensated TVSO values.

公开(公告)号：US11671099B2

公开(公告)日：2023-06-06

申请号：US17529522

申请日：2021-11-18

Applicant: Microchip Technology Inc.

Inventor： Jonathan W. Greene ,  Marcel Derevlean

IPC: H03K19/17736 ,  H03K19/17728 ,  H03K19/21

CPC classification number: H03K19/17728 ,  H03K19/17736 ,  H03K19/21

Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

公开(公告)号：US11663076B2

公开(公告)日：2023-05-30

申请号：US17825352

申请日：2022-05-26

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: G06F11/10 ,  G06F11/00 ,  H03M13/00

CPC classification number: G06F11/1048 ,  G06F11/1044

Abstract: A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.

公开(公告)号：US20230163942A1

公开(公告)日：2023-05-25

申请号：US17885194

申请日：2022-08-10

Applicant: Microchip Technology Inc.

Inventor： Scott Muma ,  Winston Mok ,  Steven Scott GORSHE

IPC: H04L7/04 ,  H04J3/06

CPC classification number: H04L7/04 ,  H04J3/0658 ,  H04L2012/5674

Abstract: A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

公开(公告)号：US11615953B2

公开(公告)日：2023-03-28

申请号：US17542303

申请日：2021-12-03

Applicant: Microchip Technology Inc.

Inventor： Amaury Gendron-Hansen ,  Bruce Odekirk

IPC: H01L21/02 ,  H01L21/04 ,  H01L27/092 ,  H01L21/67

Abstract: A silicon carbide semiconductor device includes a silicon carbide (SiC) substrate having a SiC epitaxial layer disposed over a surface of the SiC substrate, the SiC substrate having a first conductivity and the SiC epitaxial layer having the first conductivity. A contact region and a well region are formed in the SiC epitaxial layer, the contact region and the well region have a doping level of a second conductivity opposite the first conductivity. The contact region lies completely within the well region, is not in contact with a region having the first conductivity and has edges recessed from edges of the well region.

公开(公告)号：US11598654B2

公开(公告)日：2023-03-07

申请号：US17359694

申请日：2021-06-28

Applicant: Microchip Technology Inc.

Inventor： Ganesh Shaga

IPC: G01D5/20 ,  G01P3/488

Abstract: An angular position sensor comprising two annular sensors, one annular sensor for generating a coarse resolution time varying signal in the presence of a rotatable inductive coupling element and the other annular sensor for generating a fine resolution time varying signal in the presence of the rotatable inductive coupling element. The rotatable inductive coupling element comprising a first annular portion comprising at least one annular conductive sector and at least one annular non-conductive sector and a second annular portion comprising at least one annular conductive sectors and at least one annular non-conductive sector, wherein the number of annular conductive sectors of the first annular portion and the second annular portion are different. In particular, the annular conductive sectors of the annular portions may comprise 50% or 75% of the total area of the annular portions.