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    PRODUCTION METHOD OF CYST EXPRESSED TRANSGENIC ANIMAL USING PKD2 GENE
    72.
    发明申请
    PRODUCTION METHOD OF CYST EXPRESSED TRANSGENIC ANIMAL USING PKD2 GENE 审中-公开
    使用PKD2基因的CYST表达转基因动物的生产方法

    公开(公告)号：US20100281553A1

    公开(公告)日：2010-11-04

    申请号：US11814723

    申请日：2006-11-03

    Applicant: Jong-Hoon Park ,  Han-Woong Lee ,  Ji-Yeon Noh ,  Moon-Hee Yang ,  Yong-Hoon Sung ,  Tae-Young Lee

    Inventor： Jong-Hoon Park ,  Han-Woong Lee ,  Ji-Yeon Noh ,  Moon-Hee Yang ,  Yong-Hoon Sung ,  Tae-Young Lee

    IPC: A01K67/027 ,  C12N15/63

    CPC classification number: A01K67/0275 ,  A01K2217/05 ,  A01K2227/105 ,  A01K2267/035 ,  C07K14/47 ,  C12N15/8509

    Abstract: Disclosed herein is a method for producing a cyst-expressed transgenic animal using a PDK2 gene. The production method comprises preparing a PKD2 protein expression vector, inserting the expression vector into the nucleus of a fertilized egg to produce a PKD2 expression vector-containing fertilized egg, and transplanting the produced fertilized egg into the uterus of a surrogate mother. According to the invention disclosed herein, there is provided a method for producing transgenic animals, in which cysts are expressed only by the overexpression of the PKD2 gene. Also, transgenic mice are provided which can be effectively used in the investigation of cyst expression mechanisms and cyst control systems.

    Abstract translation: 本文公开了使用PDK2基因产生囊肿表达的转基因动物的方法。 制备方法包括制备PKD2蛋白表达载体，将表达载体插入受精卵的细胞核中以产生含有PKD2表达载体的受精卵，并将产生的受精卵移植到代孕母亲的子宫中。 根据本文公开的发明，提供了一种生产转基因动物的方法，其中囊肿仅通过PKD2基因的过表达来表达。 此外，提供可以有效地用于调查囊肿表达机制和囊肿控制系统的转基因小鼠。

    TAPE FEEDER FOR COMPONENT MOUNTER HAVING A PRESSURE-ACTIVATED DISCHARGE DOOR OPENING
    73.
    发明申请
    TAPE FEEDER FOR COMPONENT MOUNTER HAVING A PRESSURE-ACTIVATED DISCHARGE DOOR OPENING 有权
    配有压力开关门的组件安装带的进纸器

    公开(公告)号：US20100101079A1

    公开(公告)日：2010-04-29

    申请号：US12582894

    申请日：2009-10-21

    Applicant: Tae-Young Lee

    Inventor： Tae-Young Lee

    IPC: B23P19/00

    CPC classification number: H05K13/0417 ,  B65H20/32 ,  Y10T29/53 ,  Y10T29/53465

    Abstract: A tape feeder for supplying components to a component mounter via a carrier tape on which the components are disposed at predetermined intervals, wherein the carrier tape and components are covered with a cover tape, is described. The tape feeder may comprise a frame including a receptacle. The receptacle may have an inlet port for receiving the cover tape separated from the carrier tape, a space for containing the cover tape received through the inlet port, and a door opening through which the cover tape is discharged. The tape feeder may additionally comprise a door configured to open or close the door opening and an opening/closing member configured to fasten the door closed and thereafter open the door when an inner pressure of at least a predetermined value is applied by the cover tape received in the receptacle.

    Abstract translation: 描述了一种带式馈送器，用于经由其上以预定间隔布置组件的载带将部件提供给部件安装器，其中载带和部件被盖带覆盖。 带式给料器可以包括包括容器的框架。 容器可以具有用于接收从载带分离的盖带的入口端口，用于容纳通过入口端口容纳的盖带的空间，以及盖带从其中排出的门开口。 带式馈送器可以另外包括构造成打开或关闭门开口的门，以及打开/关闭构件，其构造成当所接收的盖带施加至少预定值的内部压力时将门闭合并且随后打开门 在容器中。

    Semiconductor devices and methods of manufacturing semiconductor devices
    74.
    发明授权
    Semiconductor devices and methods of manufacturing semiconductor devices 失效
    半导体器件和制造半导体器件的方法

    公开(公告)号：US07652354B2

    公开(公告)日：2010-01-26

    申请号：US11555381

    申请日：2006-11-01

    Applicant: Tae Young Lee

    Inventor： Tae Young Lee

    IPC: H01L21/00

    CPC classification number: H01L21/76801 ,  H01L21/76829 ,  H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed is a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an insulating layer and a metal interconnection. An insulating layer may include a first layer including fluorine and a second layer including SRO (silicon rich oxide) having a dangling bond. A metal interconnection may be formed over the insulating layer.

    Abstract translation: 公开了一种半导体器件和半导体器件的制造方法。 半导体器件可以包括绝缘层和金属互连。 绝缘层可以包括包含氟的第一层和包括具有悬挂键的SRO（富硅氧化物）的第二层。 可以在绝缘层上形成金属互连。

    Back-up table for chip mounter
    77.
    发明申请
    Back-up table for chip mounter 有权
    芯片贴片机备用桌

    公开(公告)号：US20080250630A1

    公开(公告)日：2008-10-16

    申请号：US12082032

    申请日：2008-04-08

    Applicant: Tae-Young Lee

    Inventor： Tae-Young Lee

    IPC: B23P19/00

    CPC classification number: H05K13/0069 ,  Y10T29/5313 ,  Y10T29/53135 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53187 ,  Y10T29/53961 ,  Y10T29/53974

    Abstract: A back-up table for a chip mounter. The back-up table for a chip mounter includes a base plate, a back-up plate spaced a predetermined distance from the base plate to support a back-up pin that supports a printed circuit board, and at least one set of link units installed between the base plate and the back-up plate and facing opposite to each other. The back-up table further comprises a first driving part installed between the opposite facing link units and operating the link units to raise and lower the back-up plate, and a second driving part serially connected to the first driving part.

    Abstract translation: 芯片贴片机的备用桌。 用于芯片安装器的备用台包括基板，与基板隔开预定距离的支撑板，以支撑支撑印刷电路板的支撑销，以及安装有至少一组连接单元 在基板和支撑板之间并且彼此面对。 备用桌还包括安装在相对的相对的连杆单元之间的第一驱动部分，并且操作连杆单元以升高和降低支撑板;以及与第一驱动部分串联连接的第二驱动部。

    Method for forming a dual interlayer dielectric layer of a semiconductor device
    78.
    发明申请
    Method for forming a dual interlayer dielectric layer of a semiconductor device 失效
    形成半导体器件的双层介电层的方法

    公开(公告)号：US20070155162A1

    公开(公告)日：2007-07-05

    申请号：US11644890

    申请日：2006-12-26

    Applicant: Tae Young Lee

    Inventor： Tae Young Lee

    IPC: H01L21/4763

    CPC classification number: H01L21/76837 ,  C23C16/402 ,  C23C16/505 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76829

    Abstract: A method for forming a dual interlayer dielectric layer, which is capable of preventing an interlayer delamination phenomenon generated between an etch stop layer and an interlayer dielectric layer is provided. An interlayer dielectric layer of a dual structure is formed such that a first interlayer dielectric layer and a second interlayer dielectric layer are sequentially stacked on the etch stop layer. The etch stop layer is formed on a substrate, the substrate having a source/drain region and a gate formed therein. The dual interlayer dielectric layer is selectively etched, and a conductive material is deposited thereon, thereby forming a contact. The O3-TEOS layer and the PE-TEOS layer used as the first interlayer dielectric layer can relieve a compressive stress and improve adhesion force, respectively, thereby preventing the interlayer delamination phenomenon.

    Abstract translation: 提供一种能够防止在蚀刻停止层和层间电介质层之间产生的层间分层现象的双层间电介质层的形成方法。 形成双结构的层间电介质层，使得第一层间介电层和第二层间电介质层依次层叠在蚀刻停止层上。 蚀刻停止层形成在衬底上，衬底具有源极/漏极区域和形成在其中的栅极。 选择性地蚀刻双层间介电层，并在其上沉积导电材料，从而形成接触。 用作第一层间电介质层的O 3层 - PEOS层和PE-TEOS层可以分别减轻压缩应力并提高粘合力，从而防止层间分层现象。

    Inter-metal dielectric of semiconductor device and manufacturing method thereof
    79.
    发明申请
    Inter-metal dielectric of semiconductor device and manufacturing method thereof 失效
    半导体器件的金属间电介质及其制造方法

    公开(公告)号：US20060141785A1

    公开(公告)日：2006-06-29

    申请号：US11316634

    申请日：2005-12-20

    Applicant: Tae-Young Lee

    Inventor： Tae-Young Lee

    IPC: H01L21/44 ,  H01L21/31

    CPC classification number: H01L21/76826 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/31629 ,  H01L21/76829

    Abstract: An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper line layer therein, forming a plasma enhanced fluorosilicate glass (PEFSG) layer on the first SRO layer, plasma-treating the PEFSG layer, and forming a second SRO layer on the plasma-treated PEFSG layer. According to the present invention, the thickness of the second SRO layer of the inter-metal dielectric can be reduced. Consequently, process cost can be reduced, and the total thickness of the inter-metal dielectric can be reduced so as to lower the dielectric constant thereof, reduce the aspect ratio of any via holes that are subsequently formed in the inter-metal dielectric, and potentially increase the yield as a result of the reduced via hole aspect ratio.

    Abstract translation: 根据本发明实施例的半导体器件的金属间电介质的示例性制造方法包括在其上设置有或具有铜线层的硅衬底上形成第一富硅氧化物（SRO）层，形成 在第一SRO层上的等离子体增强氟硅酸盐玻璃（PEFSG）层，等离子体处理PEFSG层，以及在等离子体处理的PEFSG层上形成第二SRO层。 根据本发明，可以减少金属间电介质的第二SRO层的厚度。 因此，可以降低工艺成本，并且可以减小金属间电介质的总厚度以降低其介电常数，减小随后在金属间电介质中形成的任何通孔的纵横比，以及 由于通孔长径比减小，潜在地提高了产量。

    Planarization method for semiconductor device
    80.
    发明授权
    Planarization method for semiconductor device 失效
    半导体器件的平面化方法

    公开(公告)号：US06348415B1

    公开(公告)日：2002-02-19

    申请号：US09472556

    申请日：1999-12-27

    Applicant: Tae Young Lee ,  Jae Suk Lee

    Inventor： Tae Young Lee ,  Jae Suk Lee

    IPC: H01L21302

    CPC classification number: H01L21/31053 ,  H01L21/3143

    Abstract: This invention discloses a planarization method for semiconductor device. The planarization method includes the steps of: providing a semiconductor substrate in which metal patterns are formed with various pattern densities; depositing a porous oxide layer over the semiconductor substrate so as to cover the metal patterns; plasma-treating surface of the porous oxide layer; and polishing the plasma-treated porous oxide layer by chemical mechanical polishing.

    Abstract translation: 本发明公开了一种半导体器件的平面化方法。 平面化方法包括以下步骤：提供其中以各种图案密度形成金属图案的半导体衬底; 在所述半导体衬底上沉积多孔氧化物层以覆盖所述金属图案; 多孔氧化物层的等离子体处理表面; 并通过化学机械抛光抛光等离子体处理的多孔氧化物层。

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