公开(公告)号：US08906805B2

公开(公告)日：2014-12-09

申请号：US13418585

申请日：2012-03-13

Applicant: Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

Inventor： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

IPC: H01L21/768 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/76802 ,  H01L21/311 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n−1 first recesses penetrating 20 through 2n−1 deposited sacrificial layers and forming a buried insulating layer group including 2n−1 buried insulating layers filling the 2n−1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n−1 buried insulating layers may be formed.

Abstract translation: 一种制造半导体器件的方法包括形成层叠结构，其中分别沉积有牺牲层的2n（n为2以上的整数）和设置在2n个沉积的牺牲层上的2n个沉积的绝缘层交替地沉积在第三 垂直于第一方向和第二方向的方向在具有在彼此垂直的第一和第二方向上延伸的上表面的基板上。 方法包括形成包括通过2n-1个沉积的牺牲层穿透20的2n-1个第一凹部的凹陷组，并且分别形成包括2n-1个第一凹部的2n-1个掩埋绝缘层的掩埋绝缘层组。 可以形成包括穿过2n个沉积绝缘层的最上层的绝缘层和2n-1个绝缘层的2n个接触插塞的接触插塞组。

公开(公告)号：US20140197481A1

公开(公告)日：2014-07-17

申请号：US14156607

申请日：2014-01-16

Applicant: Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

Inventor： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

IPC: H01L29/78

CPC classification number: H01L29/66833 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

Abstract translation: 垂直型半导体器件包括包括第一和第二字线的第一和第二字线结构。 字线围绕多个柱结构，其被提供以将字线连接到相应的字符串选择线。 连接图案将相邻的第一和第二字线的对电连接在同一平面中。 该设备可以是非易失性存储设备或不同类型的设备。

公开(公告)号：US08654585B2

公开(公告)日：2014-02-18

申请号：US13553242

申请日：2012-07-19

Applicant: Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

Inventor： Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3454

Abstract: An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.

Abstract translation: 集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。 每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。 可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。 存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

公开(公告)号：US08404578B2

公开(公告)日：2013-03-26

申请号：US13349181

申请日：2012-01-12

Applicant: Jong-Won Kim ,  Woon-Kyung Lee

Inventor： Jong-Won Kim ,  Woon-Kyung Lee

IPC: H01L21/8242

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：半导体衬底，包括单元阵列区域，设置在单元阵列区域的存储单元晶体管，设置在存储单元晶体管上的位线;以及设置在存储单元晶体管和位线之间的源极，以对存储单元晶体管 在那里

公开(公告)号：US20120281475A1

公开(公告)日：2012-11-08

申请号：US13553242

申请日：2012-07-19

Applicant: Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

Inventor： Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3454

Abstract: An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.

Abstract translation: 集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。 每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。 可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。 存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

公开(公告)号：US20120256253A1

公开(公告)日：2012-10-11

申请号：US13432485

申请日：2012-03-28

Applicant: Sung-Min Hwang ,  Woon-Kyung Lee ,  Young-Jin Kwon ,  Tae-Hee Lee ,  Hui-Chang Moon

Inventor： Sung-Min Hwang ,  Woon-Kyung Lee ,  Young-Jin Kwon ,  Tae-Hee Lee ,  Hui-Chang Moon

IPC: H01L29/78

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/7827

Abstract: Vertical memory devices include a channel, a ground selection line (GSL), a word line, a string selection line (SSL), a pad and an etch-stop layer. The channel extends in a first direction on a substrate. The channel includes an impurity region and the first direction is perpendicular to a top surface of the substrate. At least one GSL, a plurality of the word lines and at least one SSL are spaced apart from each other in the first direction on a sidewall of the channel. The pad is disposed on a top surface of the channel. The etch-stop layer contacts the pad.

Abstract translation: 垂直存储器件包括通道，接地选择线（GSL），字线，串选择线（SSL），焊盘和蚀刻停止层。 通道在基板上沿第一方向延伸。 通道包括杂质区，第一方向垂直于衬底的顶表面。 至少一个GSL，多个字线和至少一个SSL在信道的侧壁上沿第一方向彼此间隔开。 衬垫设置在通道的顶表面上。 蚀刻停止层接触焊盘。

公开(公告)号：US08243518B2

公开(公告)日：2012-08-14

申请号：US12424135

申请日：2009-04-15

Applicant: Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

Inventor： Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3454

Abstract: An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.

Abstract translation: 集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。 每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。 可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。 存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

公开(公告)号：US20120193705A1

公开(公告)日：2012-08-02

申请号：US13285291

申请日：2011-10-31

Applicant: Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

Inventor： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

IPC: H01L29/78 ,  H01L23/48

CPC classification number: G11C16/0483 ,  G11C5/025 ,  G11C5/063 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

Abstract translation: 存储器件包括其中限定有单元阵列区域的衬底。 在单元阵列区域的边界附近设置在基板上或基板上的虚设结构。 存储器件还包括设置在单元阵列区域中的衬底上的垂直沟道区域。 所述存储装置还包括多个垂直堆叠的导电栅极线，其间插入有绝缘层，所述导电栅极线和插入的绝缘层横向设置在所述垂直沟道区域的两侧并延伸穿过所述虚拟结构，所述至少一个所述导电栅极 线和绝缘层，其在被配置为用作参考特征的虚拟结构的交叉处具有表面变化。 虚拟结构可以包括沟槽，并且表面变化可以包括覆盖沟槽的凹陷。

公开(公告)号：US08187967B2

公开(公告)日：2012-05-29

申请号：US12458675

申请日：2009-07-20

Applicant: Seung-jun Lee ,  Woon-kyung Lee ,  Seung-wan Hong

Inventor： Seung-jun Lee ,  Woon-kyung Lee ,  Seung-wan Hong

IPC: H01L21/4763

CPC classification number: H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568

Abstract: A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on the cell region and the peripheral region, forming a trench for exposing a portion of the first conductive layer of the peripheral region, wherein the trench is formed by removing portions of the second conductive layer and the second insulating layer in the peripheral region, performing a trimming operation for removing portions of the second conductive layer and the second insulating layer of the cell region, forming a spacer on a side surface of the trench, and forming a silicide layer that is electrically connected to the first conductive layer, wherein the silicide layer is formed by performing a silicidation process on the spacer.

Abstract translation: 一种制造提供其中限定了单元区域和外围区域的半导体层的非易失性存储器件的方法，其顺序地形成在第一绝缘层，第一导电层，第二绝缘层和第二导电层上 形成用于暴露周边区域的第一导电层的一部分的沟槽，其中通过去除周边区域中的第二导电层和第二绝缘层的部分形成沟槽，进行修整 用于去除所述第二导电层和所述单元区域的所述第二绝缘层的部分的工作，在所述沟槽的侧表面上形成间隔物，以及形成电连接到所述第一导电层的硅化物层，其中所述硅化物层为 通过在间隔物上进行硅化处理而形成。

公开(公告)号：US20120007193A1

公开(公告)日：2012-01-12

申请号：US13240575

申请日：2011-09-22

Applicant: Jin-Sung Lee ,  Woon-Kyung Lee

Inventor： Jin-Sung Lee ,  Woon-Kyung Lee

IPC: H01L27/088

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573

Abstract: A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.

Abstract translation: 半导体器件包括设置在半导体衬底上的多个晶体管，围绕晶体管设置的器件隔离层，设置成围绕器件隔离层和晶体管的保护环以及设置在相邻晶体管之间的保护区。