Programming schemes for multi-level analog memory cells
    71.
    发明授权
    Programming schemes for multi-level analog memory cells 有权
    多级模拟存储单元的编程方案

    公开(公告)号:US09449705B2

    公开(公告)日:2016-09-20

    申请号:US14173965

    申请日:2014-02-06

    Applicant: Apple Inc.

    Abstract: A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

    Abstract translation: 一种用于数据存储的方法包括:通过对存储器单元进行编程来采用各自的第一编程级别,来将第一数据位在第一时间存储在一组多位模拟存储单元中。 第二数据位通过对存储器单元进行编程以采取依赖于第一编程电平和第二数据位的相应的第二编程电平而在比第一时间晚的第二时间存储在存储单元组中。 响应于第一次和第二次之间的差异选择存储策略。 将存储策略应用于从第一数据位和第二数据位中选择的至少一组数据位。

    Power-optimized decoding of linear codes

    公开(公告)号:US09337955B2

    公开(公告)日:2016-05-10

    申请号:US13965508

    申请日:2013-08-13

    Applicant: Apple Inc.

    Abstract: A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.

    MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION
    73.
    发明申请
    MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION 审中-公开
    在长期静态和擦除状态下,减轻模拟记忆细胞的可靠性降低

    公开(公告)号:US20160093386A1

    公开(公告)日:2016-03-31

    申请号:US14962333

    申请日:2015-12-08

    Applicant: Apple Inc.

    Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

    Abstract translation: 一种非易失性存储器中的方法,其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元,包括接收指示要保留的一组存储器单元的存储操作,而不进行编程 长时间 组中的存储单元被设置为与擦除的电平不同的保持编程电平。 在准备使用数据对存储器单元组进行编程时,存储器单元组被擦除到擦除的电平,然后将数据编程在存储器单元组中。

    ESTIMATING FLASH QUALITY USING SELECTIVE ERROR EMPHASIS
    74.
    发明申请
    ESTIMATING FLASH QUALITY USING SELECTIVE ERROR EMPHASIS 有权
    使用选择性错误来评估闪光质量

    公开(公告)号:US20160092284A1

    公开(公告)日:2016-03-31

    申请号:US14501081

    申请日:2014-09-30

    Applicant: APPLE INC.

    Abstract: A method for data storage includes reading from a memory device data that is stored in a group of memory cells as respective analog values, and classifying readout errors in the read data into at least first and second different types, depending on zones in which the analog values fall. A memory quality that emphasizes the readout errors of the second type is assigned to the group of the memory cells, based on evaluated numbers of the readout errors of the first and second types.

    Abstract translation: 一种用于数据存储的方法包括:从存储器件读取作为相应模拟值存储在一组存储器单元中的数据,并将读出的数据中的读出错误分类为至少第一和第二不同类型,这取决于模拟 价值下降。 基于第一和第二类型的读出错误的评估数,将强调第二类型的读出错误的存储器质量分配给存储器单元组。

    Distortion estimation and cancellation in memory devices

    公开(公告)号:US09292381B2

    公开(公告)日:2016-03-22

    申请号:US14090431

    申请日:2013-11-26

    Applicant: Apple Inc.

    CPC classification number: G06F11/1068 G06F11/1016 G11C16/26

    Abstract: A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.

    Efficient LDPC codes
    77.
    发明授权
    Efficient LDPC codes 有权
    高效的LDPC码

    公开(公告)号:US09075738B2

    公开(公告)日:2015-07-07

    申请号:US14090498

    申请日:2013-11-26

    Applicant: Apple Inc.

    Abstract: A method includes accepting a definition of a mother Error Correction Code (ECC) that is represented by a set of parity check equations and includes first code words, and a definition of a punctured ECC that includes second code words and is derived from the mother ECC by removal of one or more of the parity check equations and removal of one or more punctured check symbols selected from among check symbols of the first code words. A mother decoder, which is designed to decode the mother ECC by exchanging messages between symbol nodes and check nodes in accordance with a predefined interconnection scheme that represents the mother ECC, is provided. An input code word of the punctured ECC is decoded using the mother decoder by initializing one or more of the symbol nodes and controlling one or more of the messages, and while retaining the interconnection scheme.

    Abstract translation: 一种方法包括接受由一组奇偶校验方程表示的母体误差校正码(ECC)的定义,并且包括第一码字和包括第二码字并从母体ECC导出的穿孔ECC的定义 通过去除一个或多个奇偶校验方程和从第一码字的检查符号中选出的一个或多个穿孔校验符号的去除。 提供了一种母版解码器,其被设计为通过根据表示母ECC的预定互连方案在符号节点和校验节点之间交换消息来解码母ECC。 通过初始化符号节点中的一个或多个并控制消息中的一个或多个,同时保留互连方案,使用母版解码器解码穿孔ECC的输入码字。

    Data Storage Management in Analog Memory Cells Using a Non-Integer Number of Bits Per Cell
    78.
    发明申请
    Data Storage Management in Analog Memory Cells Using a Non-Integer Number of Bits Per Cell 有权
    使用非整数每个单元的位数模拟存储单元中的数据存储管理

    公开(公告)号:US20150179265A1

    公开(公告)日:2015-06-25

    申请号:US14135881

    申请日:2013-12-20

    Applicant: Apple Inc.

    Abstract: A method for data storage includes, in a first programming phase, storing first data in a group of memory cells by programming the memory cells in the group to a set of initial programming levels. In a subsequent second programming phase, second data is stored in the group by identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels, and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels. The memory cells to which the second data was programmed are recognized by reading only a partial subset of the first data. The second data is read from the recognized memory cells.

    Abstract translation: 一种用于数据存储的方法包括在第一编程阶段中通过将组中的存储器单元编程为一组初始编程级别来将第一数据存储在一组存储器单元中。 在随后的第二编程阶段,通过将在第一编程阶段中编程的组中的存储器单元识别为初始编程级的预定义部分子集中的相应级别,并且仅编程所识别的存储器,将第二数据存储在组中 具有第二数据的单元,以便将所识别的存储器单元中的至少一些设置为与初始编程电平不同的一个或多个附加编程电平。 通过仅读取第一数据的部分子集来识别第二数据被编程到的存储器单元。 从识别的存储器单元读取第二数据。

    Efficient re-read operations in analog memory cell arrays
    79.
    发明授权
    Efficient re-read operations in analog memory cell arrays 有权
    模拟存储单元阵列中的高效重读操作

    公开(公告)号:US08990659B2

    公开(公告)日:2015-03-24

    申请号:US14330203

    申请日:2014-07-14

    Applicant: Apple Inc.

    Abstract: A method for data storage includes storing data, which is encoded with an Error Correction Code (ECC), in a group of analog memory cells by writing respective first storage values to the memory cells in the group. After storing the data, respective second storage values are read from the memory cells in the group, and the read second storage values are processed so as to decode the ECC. Responsively to a failure in decoding the ECC, one or more of the second storage values that potentially caused the failure are identified as suspect storage values. Respective third storage values are re-read from a subset of the memory cells that includes the memory cells holding the suspect storage values. The ECC is re-decoded using the third storage values so as to reconstruct the stored data.

    Abstract translation: 一种用于数据存储的方法包括通过将相应的第一存储值写入组中的存储器单元来将经错误校正码(ECC)编码的数据存储在一组模拟存储器单元中。 在存储数据之后,从组中的存储器单元读取相应的第二存储值,并且处理读取的第二存储值以便对ECC进行解码。 响应于对ECC的解码失败,可​​能导致故障的一个或多个第二存储值被识别为可疑存储值。 从包含存储可疑存储值的存储单元的存储器单元的子集重新读取相应的第三存储值。 使用第三存储值对ECC进行重新解码,以重建存储的数据。

Patent Agency Ranking