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    ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME
    71.
    发明申请
    ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME 有权
    电子设备，其中包括一个TRENCH和一个导电结构及其形成过程

    公开(公告)号：US20130221436A1

    公开(公告)日：2013-08-29

    申请号：US13404895

    申请日：2012-02-24

    申请人： Zia Hossain ,  Gordon M. Grivna

    发明人： Zia Hossain ,  Gordon M. Grivna

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L29/7827 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

    摘要： An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device.

    摘要翻译： 电子器件可以包括晶体管结构，其包括覆盖在衬底上并具有主表面的图案化半导体层。 电子器件还可以包括在第一沟槽和第二沟槽的每一个内的第一导电结构，第一沟槽内的栅电极和与第一导电结构电绝缘的第一绝缘构件，设置在栅电极和第一导电结构之间 在第一沟槽内，以及在第二沟槽内的第二导电结构。 第二导电结构可以电连接到第一导电结构并且与栅电极电绝缘。 电子设备还可以包括设置在第二导电结构和第二沟槽内的第一导电结构之间的第二绝缘构件。 可以使用简化电子设备内的特征的形成的处理顺序。

    ELECTRONIC DEVICE INCLUDING A WELL REGION
    75.
    发明申请
    ELECTRONIC DEVICE INCLUDING A WELL REGION 有权
    电子设备，包括一个良好的地区

    公开(公告)号：US20120112278A1

    公开(公告)日：2012-05-10

    申请号：US13353223

    申请日：2012-01-18

    申请人： Gary H. Loechelt ,  Gordon M. Grivna

    发明人： Gary H. Loechelt ,  Gordon M. Grivna

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823892 ,  H01L21/2815 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region.

    摘要翻译： 包括集成电路的电子设备可以包括掩埋导电区域和覆盖掩埋导电区域的半导体层，以及延伸穿过半导体层并电连接到掩埋导电区域的垂直导电结构。 集成电路还可以包括与掩埋导电区相比具有相对导电类型的掺杂结构，其比与半导体层的主表面更接近于相对表面，并且电连接到掩埋导电区。 集成电路还可以包括包括半导体层的一部分的阱区，其中该部分覆盖掺杂结构并且与掺杂结构相比具有较低的掺杂剂浓度。 在另一个实施例中，掺杂结构可以与掩埋的导电区域间隔开。

    ELECTRONIC DEVICE INCLUDING A FEATURE IN A TRENCH
    76.
    发明申请
    ELECTRONIC DEVICE INCLUDING A FEATURE IN A TRENCH 有权
    电子设备，其中包括在TRENCH中的功能

    公开(公告)号：US20120049320A1

    公开(公告)日：2012-03-01

    申请号：US12871390

    申请日：2010-08-30

    申请人： John Michael Parsey, JR. ,  Gordon M. Grivna

    发明人： John Michael Parsey, JR. ,  Gordon M. Grivna

    IPC分类号： H01L21/82 ,  H01L21/768

    CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L27/0207 ,  H01L28/10 ,  H01L28/20 ,  H01L28/91 ,  H01L29/6609 ,  H01L29/66106 ,  H01L29/861 ,  H01L29/866 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/00

    摘要： A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows.

    摘要翻译： 半导体衬底可以被图案化以限定沟槽和特征。 在一个实施例中，可以形成沟槽，使得在用材料填充沟槽之后，填充沟槽的底部部分可以在衬底变薄操作期间暴露。 在另一个实施例中，沟槽可以用热氧化物填充。 该特征可以具有减小在后续处理期间在特征和沟槽的壁之间的距离将被改变的可能性的形状。 结构可以至少部分地形成在沟槽内，其中通过利用沟槽的深度，该结构可以具有相对大的面积。 该结构可用于制造电子部件，例如无源部件和贯穿基板通孔。 定义沟槽和形成结构的过程顺序可以针对许多不同的工艺流程进行定制。

    METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE
    78.
    发明申请
    METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE 有权
    形成具有屏蔽电极结构的绝缘栅场效应晶体管器件的方法

    公开(公告)号：US20110136310A1

    公开(公告)日：2011-06-09

    申请号：US12633967

    申请日：2009-12-09

    申请人： Gordon M. Grivna

    发明人： Gordon M. Grivna

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7811 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813

    摘要： A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and dielectric plugs are formed in the first recessed regions using the first layer as a stop layer. The first layer is then removed, and spacers are formed adjacent the dielectric plugs. Second recessed regions are formed in the substrate self-aligned to the spacers.

    摘要翻译： 在沟槽区域内形成具有绝缘栅电极和绝缘屏蔽电极的晶体管的方法包括形成覆盖在衬底上的电介质叠层。 电介质堆叠包括覆盖衬底的一种材料的第一层和覆盖第一层的不同材料的第二层。 沟槽区域形成在与电介质叠层相邻的位置。 在形成绝缘屏蔽电极之后，该方法包括去除第二层，然后形成绝缘栅电极。 去除部分栅电极材料以形成第一凹陷区域，并且使用第一层作为停止层在第一凹陷区域中形成介电塞。 然后去除第一层，并且在电介质塞附近形成间隔物。 在与衬垫自对准的衬底中形成第二凹陷区域。