公开(公告)号：US09105654B2

公开(公告)日：2015-08-11

申请号：US13426106

申请日：2012-03-21

申请人： Ta-Chun Ma ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Ta-Chun Ma ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/3083 ,  H01L29/045 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7851 ,  H01L29/7853

摘要： An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate.

摘要翻译： 一个实施例是FinFET器件。 FinFET器件包括鳍片，第一源极/漏极区域，第二源极/漏极区域和沟道区域。 翅片升高到基底之上。 第一源/漏区和第二源极/漏极区在鳍中。 沟道区域横向在第一和第二源极/漏极区域之间。 沟道区域具有不平行且不垂直于衬底顶表面的刻面。

公开(公告)号：US09054188B2

公开(公告)日：2015-06-09

申请号：US13404819

申请日：2012-02-24

申请人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

发明人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

IPC分类号： H01L21/3205 ,  H01L21/683 ,  H01L21/687 ,  H01L21/31 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L21/687 ,  H01L21/6838 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

摘要： An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.

摘要翻译： 提供了一种形成半导体结构的装置和方法。 该装置包括：基板保持件，其保持基板，使得处理表面是弯曲的，例如凸形或凹形。 基板使用点接触保持就位，多个连续接触部分围绕基板延伸，和/或完全围绕基板延伸的连续环。 处理可以包括例如形成源极/漏极区域，沟道区域，硅化物，应力存储层等。

公开(公告)号：US09006802B2

公开(公告)日：2015-04-14

申请号：US13212834

申请日：2011-08-18

申请人： Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

发明人： Gin-Chen Huang ,  Tsai-Fu Hsiao ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Hongfa Luan ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/02274 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/324 ,  H01L29/66795

摘要： Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

摘要翻译： 公开了形成绝缘材料层的半导体器件制造方法和方法。 在一个实施例中，形成半导体器件的复合绝缘材料层的方法包括提供工件并使用第一等离子体功率电平在工件上形成绝缘材料层的第一子层。 使用第二等离子体功率电平在绝缘材料层的第一子层上形成绝缘材料层的第二子层，并且将工件退火。

公开(公告)号：US08962400B2

公开(公告)日：2015-02-24

申请号：US13178294

申请日：2011-07-07

申请人： Ji-Yin Tsai ,  Yao-Tsung Huang ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Ji-Yin Tsai ,  Yao-Tsung Huang ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/84 ,  H01L21/8234 ,  H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/36 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66795 ,  Y10S438/933

摘要： A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.

摘要翻译： 一种方法包括在半导体区域上形成栅极叠层，并使半导体区域凹陷以形成邻近栅叠层的凹陷。 在凹部中外延生长含硅半导体区域以形成源极/漏极应力源。 在外延生长含硅半导体区域的步骤期间，砷原位被掺杂。

公开(公告)号：US08674341B2

公开(公告)日：2014-03-18

申请号：US12639653

申请日：2009-12-16

申请人： Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/336

CPC分类号： H01L29/8124 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/66431 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/812

摘要： A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.

摘要翻译： 多栅极晶体管包括在衬底上的半导体鳍。 半导体鳍片包括由第一半导体材料形成的中心鳍片; 以及半导体层，其具有在中心散热片的相对侧壁上的第一部分和第二部分。 半导体层包括与第一半导体材料不同的第二半导体材料。 多栅极晶体管还包括围绕半导体鳍片的侧壁的栅电极; 以及在半导体鳍片的相对端上的源极区域和漏极区域。 中央翅片和半导体层中的每一个从源极区域延伸到漏极区域。

公开(公告)号：US08618556B2

公开(公告)日：2013-12-31

申请号：US13174170

申请日：2011-06-30

申请人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Yao-Tsung Huang ,  Clement Hsingjen Wann

发明人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Yao-Tsung Huang ,  Clement Hsingjen Wann

IPC分类号： H01L29/24 ,  H01L29/26

CPC分类号： H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/785

摘要： An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures.

摘要翻译： 公开了一种集成电路器件及其制造方法。 示例性器件包括具有衬底表面的半导体衬底和设置在半导体衬底中的用于隔离器件的NMOS区域和器件的PMOS区域的沟槽隔离结构。 该器件还包括第一鳍结构，其包括设置在具有高带隙能量和晶格常数大于Ge的III-V半导体材料的层上的硅或SiGe; 包括硅或SiGe的第二鳍结构，其设置在具有高带隙能量和比Ge小的晶格常数的III-V半导体材料层上; 以及设置在垂直于第一和第二鳍结构并且布置在其上的栅极结构。

公开(公告)号：US20130234147A1

公开(公告)日：2013-09-12

申请号：US13415339

申请日：2012-03-08

申请人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L29/205 ,  H01L21/20 ,  H01L29/06

CPC分类号： H01L29/7851 ,  H01L21/0259 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/76224 ,  H01L21/8252 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785

摘要： An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.

公开(公告)号：US20130210212A1

公开(公告)日：2013-08-15

申请号：US13396515

申请日：2012-02-14

申请人： Chih-Hui Weng ,  Wei-Sheng Yun ,  Shao-Ming Yu ,  Hsin-Chih Chen ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Chih-Hui Weng ,  Wei-Sheng Yun ,  Shao-Ming Yu ,  Hsin-Chih Chen ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L21/823412 ,  H01L21/3083 ,  H01L21/32 ,  H01L21/823418 ,  H01L21/823481 ,  H01L25/50 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece.

摘要翻译： 公开了制造半导体器件的方法。 在一个实施例中，制造半导体器件的方法包括提供工件，以及在工件的底表面和边缘上形成保护材料。 加工工件的顶面。 保护材料在加工工件的上表面时保护工件的边缘和底面。

公开(公告)号：US08497201B2

公开(公告)日：2013-07-30

申请号：US13268191

申请日：2011-10-07

申请人： Tsung-Lin Lee ,  Clement Hsingjen Wann ,  Ching-Yu Chang

发明人： Tsung-Lin Lee ,  Clement Hsingjen Wann ,  Ching-Yu Chang

IPC分类号： H01L21/4763

CPC分类号： H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

摘要： A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.

摘要翻译： 提供一种制造半导体器件的方法，其包括提供衬底。 材料层形成在衬底上。 聚合物层形成在材料层上。 使用聚合物层的一部分自组装纳米尺寸的特征。 使用纳米尺寸的特征对衬底进行图案化。

公开(公告)号：US08470659B2

公开(公告)日：2013-06-25

申请号：US13595599

申请日：2012-08-27

申请人： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

发明人： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC分类号： H01L21/8249

CPC分类号： H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

摘要： This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

摘要翻译： 该描述涉及包括在半导体衬底上形成界面层的方法。 该方法还包括蚀刻回界面层。 该方法还包括在界面层上进行紫外线（UV）固化过程。 UV固化方法包括将每分钟10标准立方厘米（sccm）的气体流速提供到5标准升/分钟（slm），其中气体包括惰性气体，并且在小于或等于的温度下加热界面层 至700℃。该方法还包括在界面层上沉积高k介电材料。