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公开(公告)号：US20130248948A1
公开(公告)日：2013-09-26
申请号：US13426106
申请日：2012-03-21
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02639 , H01L21/30604 , H01L21/3083 , H01L29/045 , H01L29/0688 , H01L29/1037 , H01L29/66636 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7833 , H01L29/7851 , H01L29/7853
摘要： An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate.
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公开(公告)号：US09105654B2
公开(公告)日：2015-08-11
申请号：US13426106
申请日：2012-03-21
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/02639 , H01L21/30604 , H01L21/3083 , H01L29/045 , H01L29/0688 , H01L29/1037 , H01L29/66636 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7833 , H01L29/7851 , H01L29/7853
摘要： An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate.
摘要翻译： 一个实施例是FinFET器件。 FinFET器件包括鳍片，第一源极/漏极区域，第二源极/漏极区域和沟道区域。 翅片升高到基底之上。 第一源/漏区和第二源极/漏极区在鳍中。 沟道区域横向在第一和第二源极/漏极区域之间。 沟道区域具有不平行且不垂直于衬底顶表面的刻面。
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公开(公告)号：US08716765B2
公开(公告)日：2014-05-06
申请号：US13428972
申请日：2012-03-23
IPC分类号： H01L29/94
CPC分类号： H01L29/66545 , H01L21/02609 , H01L21/28506 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66636 , H01L29/78 , H01L29/7848 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A contact structure for a semiconductor device includes a substrate comprising a major surface and a cavity. A bottom surface of the cavity is lower than the major surface. The contact structure also includes a strained material in the cavity, and a lattice constant of the strained material is different from lattice constant of the substrate. The contact structure also includes a first metal layer over the strained material, a dielectric layer over the first metal layer, and a second metal layer over the dielectric layer. The dielectric layer has a thickness ranging from 1 nm to 10 nm.
摘要翻译： 用于半导体器件的接触结构包括包括主表面和腔的衬底。 空腔的底面低于主面。 接触结构还包括空腔中的应变材料，并且应变材料的晶格常数不同于衬底的晶格常数。 接触结构还包括应变材料上的第一金属层，第一金属层上的电介质层和介电层上的第二金属层。 电介质层的厚度范围为1nm至10nm。
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公开(公告)号：US20130119405A1
公开(公告)日：2013-05-16
申请号：US13295178
申请日：2011-11-14
IPC分类号： H01L29/772
CPC分类号： H01L29/0847 , H01L21/76224 , H01L29/66575 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.
摘要翻译： 本发明提供一种半导体器件。 半导体器件包括半导体衬底。 半导体器件包括设置在衬底上的栅极。 基板具有凹部。 半导体器件包括沿着凹部涂覆的沟槽衬垫。 沟槽衬垫包含半导体晶体材料。 沟槽衬垫直接邻接源极/漏极应力器件。 半导体器件还包括设置在沟槽衬垫上并填充凹槽的电介质沟槽部件。 半导体器件包括设置在衬底中的源极/漏极应力器件。 源极/漏极应力器件设置在栅极和沟槽衬垫之间。
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5.发明授权公开(公告)号：US08242540B2
公开(公告)日：2012-08-14
申请号：US12813822
申请日：2010-06-11
IPC分类号： H01L21/02
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02639 , H01L21/3247 , H01L21/76224 , H01L29/20 , H01L29/66522 , H01L29/78
摘要： A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm.
摘要翻译： 一种器件包括硅衬底以及与硅衬底接触的III-V族化合物半导体区域。 III-V族化合物半导体区域具有与硅衬底的U形界面，U形界面的半径小于约1000nm。
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6.发明申请公开(公告)号：US20110304021A1
公开(公告)日：2011-12-15
申请号：US12813822
申请日：2010-06-11
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02639 , H01L21/3247 , H01L21/76224 , H01L29/20 , H01L29/66522 , H01L29/78
摘要： A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm.
摘要翻译： 一种器件包括硅衬底以及与硅衬底接触的III-V族化合物半导体区域。 III-V族化合物半导体区域具有与硅衬底的U形界面，U形界面的半径小于约1000nm。
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7.发明申请Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers 有权生长III-V化合物半导体从填充中间层的沟槽公开(公告)号：US20110117730A1
公开(公告)日：2011-05-19
申请号：US12842221
申请日：2010-07-23
IPC分类号： H01L21/20
CPC分类号： H01L21/02647 , H01L21/02381 , H01L21/02389 , H01L21/02458 , H01L21/02463 , H01L21/0254 , H01L21/02546 , H01L21/02617 , H01L21/02639
摘要： A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.
摘要翻译： 形成集成电路结构的方法包括在衬底的至少一部分上形成绝缘层; 在所述绝缘层的顶表面上形成多个半导体柱。 多个半导体柱由绝缘层的一部分水平隔开。 以周期性图案分配多个半导体柱。 该方法还包括从半导体柱的顶表面和侧壁外延生长III-V族化合物半导体膜。
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公开(公告)号：US08629012B2
公开(公告)日：2014-01-14
申请号：US13595797
申请日：2012-08-27
申请人： Heng-Kuang Lin , Pei-Chin Chiu , Jen-Inn Chyi , Han-Chieh Ho , Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
发明人： Heng-Kuang Lin , Pei-Chin Chiu , Jen-Inn Chyi , Han-Chieh Ho , Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
IPC分类号： H01L21/338
CPC分类号： H01L29/205 , B82Y10/00 , H01L21/8252 , H01L27/085 , H01L27/0883 , H01L27/092 , H01L29/122 , H01L29/42316 , H01L29/42356 , H01L29/66462 , H01L29/7783
摘要： An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.
摘要翻译： 集成电路结构包括基板和第一和第二多个III-V半导体层。 所述第一多个III-V半导体层包括在所述衬底上的第一底部阻挡层; 在第一底部屏障上的第一通道层; 以及第一通道层上的第一顶部势垒。 第一场效应晶体管（FET）包括第一沟道区，其包括第一沟道层的一部分。 第二多个III-V半导体层在第一多个III-V半导体层之上，并且包括第二底部屏障; 在第二底部屏障上的第二通道层; 以及在第二通道层上的第二顶部阻挡层。 第二FET包括第二沟道区，其包括第二沟道层的一部分。
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9.发明授权公开(公告)号：US08609517B2
公开(公告)日：2013-12-17
申请号：US12814088
申请日：2010-06-11
CPC分类号： H01L21/0262 , C30B25/105 , C30B25/186 , C30B29/40 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02538 , H01L21/02639 , H01L21/76224
摘要： A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).
摘要翻译： 一种器件包括提供硅衬底; 在高于约900℃的第一温度下退火硅衬底; 以及将所述硅衬底的温度从所述第一温度降低到第二温度。 在降低温度的步骤期间的降温速率大于约1℃/秒。 使用金属有机化学气相沉积（MOCVD）在硅衬底的表面上外延生长III-V族化合物半导体区域。
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公开(公告)号：US08486770B1
公开(公告)日：2013-07-16
申请号：US13340937
申请日：2011-12-30
IPC分类号： H01L21/335
CPC分类号： H01L27/1211 , H01L21/823821 , H01L21/8258 , H01L21/845 , H01L29/1054 , H01L29/267
摘要： A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.
摘要翻译： 公开了一种用于制造CMOS FinFET器件的CMOS FinFET器件和方法。 示例性的CMOS FinFET器件包括包括第一区域和第二区域的衬底。 CMOS FinFET还包括布置在衬底上的翅片结构，其包括在第一区域中的第一鳍片和在第二区域中的第二鳍片。 CMOS FinFET还包括第一鳍片的第一部分，其包括与衬底相同的材料的材料，以及第一鳍片的第二部分，其包括沉积在第一鳍片的第一部分上的III-V半导体材料。 CMOS FinFET还包括第二鳍片的第一部分，其包括与衬底相同的材料，第二鳍片的第二部分包括沉积在第二鳍片的第一部分上的锗（Ge）材料。
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