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112 条记录 (耗时 0.024 秒)

    Structure and method for topography free SOI integration
    71.
    发明授权
    Structure and method for topography free SOI integration 有权
    地形自由SOI集成的结构和方法

    公开(公告)号：US08936996B2

    公开(公告)日：2015-01-20

    申请号：US12958429

    申请日：2010-12-02

    申请人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

    发明人： Ravi M. Todi ,  Joseph Ervin ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L21/76 ,  H01L29/02 ,  H01L21/762

    CPC分类号： H01L29/02 ,  H01L21/76254

    摘要： A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

    摘要翻译： 提供了包括具有特征的半导体氧化物层的半导体结构。 具有特征的半导体氧化物层位于有源半导体层和手柄基板之间。 半导体结构包括有源半导体层的平坦化顶表面，使得半导体氧化物层位于平坦化的顶表面之下。 半导体氧化物层内的特征与有源半导体层的表面配合。

    Reliable electrical fuse with localized programming
    73.
    发明授权
    Reliable electrical fuse with localized programming 有权
    可靠的电熔丝与本地编程

    公开(公告)号：US08896088B2

    公开(公告)日：2014-11-25

    申请号：US13095164

    申请日：2011-04-27

    申请人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

    发明人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

    IPC分类号： H01L23/52 ,  H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/12 ,  G11C17/16

    CPC分类号： H01L23/62 ,  G11C17/16 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76886 ,  H01L21/823814 ,  H01L21/84 ,  H01L23/5256 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.

    摘要翻译： 电熔丝在半导体衬底的表面上具有阳极接触。 电熔丝在半导体衬底的与阳极接触件间隔开的表面上具有阴极接触。 电熔丝在衬底内具有连接阳极接触件和阴极接触件的连接。 该连接件包括半导体层和硅化物层。 硅化物层延伸超过阳极接触。 硅化物层的另一端延伸超过阴极接触。 在硅化物层之下的阳极接触和阴极接触之间的半导体层中嵌入硅锗区。

    SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY
    75.
    发明申请
    SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY 有权
    使用固体相外延片的子图形宽度FINFET

    公开(公告)号：US20140061793A1

    公开(公告)日：2014-03-06

    申请号：US13597752

    申请日：2012-08-29

    申请人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    发明人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L21/336

    CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

    摘要： A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

    摘要翻译： 介电心轴结构形成在单晶半导体层上。 非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。 可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。 在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。 外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。 在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

    Field effect transistors with low body resistance and self-balanced body potential
    77.
    发明授权
    Field effect transistors with low body resistance and self-balanced body potential 有权
    具有低体电阻和自平衡体电位的场效应晶体管

    公开(公告)号：US08564069B1

    公开(公告)日：2013-10-22

    申请号：US13590212

    申请日：2012-08-21

    申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/088

    CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/027 ,  H01L29/0615 ,  H01L29/78

    摘要： Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share same body potential. In one embodiment, the invention includes a field effect transistor (FET) comprising a source within a substrate, a drain within the substrate, and an active gate atop the substrate and between the source and the drain, an inactive gate structure atop the substrate and adjacent the source or the drain, a body adjacent the inactive gate, and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate.

    摘要翻译： 本发明的实施例大体上涉及半导体器件，更具体地，涉及具有低体电阻的场效应晶体管（FET）的半导体器件，在一些实施例中，具有多个晶体管共享相同体电位的自平衡体电位。 在一个实施例中，本发明包括场效应晶体管（FET），其包括在衬底内的源极，衬底内的漏极，以及位于衬底顶部和源极与漏极之间的有源栅极，在衬底顶部的非活性栅极结构， 邻近源极或漏极，与非活性栅极相邻的主体以及衬底内的用于从FET释放电荷的放电路径，放电路径位于FET的有源栅极和主体之间，其中放电路径基本上 垂直于有源栅极的宽度。

    Polysilicon resistor and E-fuse for integration with metal gate and high-k dielectric
    78.
    发明授权
    Polysilicon resistor and E-fuse for integration with metal gate and high-k dielectric 有权
    用于与金属栅极和高k电介质集成的多晶硅电阻器和电熔丝

    公开(公告)号：US08481397B2

    公开(公告)日：2013-07-09

    申请号：US12719289

    申请日：2010-03-08

    申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Rainer Loesing ,  Chengwen Pei ,  Xiaojun Yu

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Rainer Loesing ,  Chengwen Pei ,  Xiaojun Yu

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/525 ,  H01L29/12 ,  H01L29/86 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.

    摘要翻译： 提供了一种用于制造电阻性多晶半导体器件的方法，例如诸如半导体集成电路的微电子元件的多晶硅电阻器。 该方法可以包括：（a）形成层叠堆叠，其包括与衬底的单晶半导体区域的表面接触的电介质层，覆盖在电介质层上的金属栅极层，与金属栅极层相邻的第一多晶半导体区域， 掺杂剂类型的n或p，以及第二多晶半导体区域，其与所述第一多晶半导体区域与所述金属栅极层隔开并邻接所述第一多晶半导体区域; 和（b）形成与所述第二多晶半导体区域导电连通的第一和第二触点，所述第一和第二触点间隔开以达到期望的电阻。 在其变型中，形成电熔丝，其包括连续的硅化物区域，电流可以通过该硅化物区域通过以熔断熔丝。 在同一衬底上制造金属栅极场效应晶体管（FET）的同时可以同时采用制造多晶硅电阻器或电熔丝的步骤。

    Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices
    79.
    发明申请
    Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices 有权
    嵌入式半导体绝缘体器件的单晶硅和漏极

    公开(公告)号：US20130105898A1

    公开(公告)日：2013-05-02

    申请号：US13285162

    申请日：2011-10-31

    申请人： Geng Wang ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

    发明人： Geng Wang ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/84 ,  H01L27/1203

    摘要： After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.

    摘要翻译： 在形成栅极叠层之后，要形成源极和漏极的区域通过顶部半导体层凹陷，并进入绝缘体上半导体（SOI）的掩埋的单晶稀土氧化物层的上部， 衬底，从而形成源极沟槽和漏极沟槽。 在源极沟槽和漏极沟槽的每一个中分别形成外延对齐于埋入的单晶稀土氧化物层的嵌入式单晶半导体部分，以分别形成凹陷源和凹陷漏极。 可以将栅极电介质的底表面之上的凹陷源和凹陷漏极的突起最小化，以减少与栅极电极的寄生电容耦合，同时通过凹陷源和凹陷漏极的增加的厚度提供低的源极电阻和漏极电阻，相对于 顶部半导体层的厚度。