公开(公告)号：US20150084207A1

公开(公告)日：2015-03-26

申请号：US14037728

申请日：2013-09-26

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/522 ,  H01L23/42 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

公开(公告)号：US20150069612A1

公开(公告)日：2015-03-12

申请号：US14547667

申请日：2014-11-19

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3178 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L24/95 ,  H01L25/072 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2224/92144 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.

Abstract translation: 公开了一种表面贴装封装结构，其提供了改善的热机械可靠性和更坚固的二级封装互连。 表面贴装封装结构包括具有电介质层的子模块，附着到电介质层的半导体器件，电耦合到半导体器件的第一级金属互连结构以及电耦合到第一级的第二级I / O连接 互连并形成在与半导体器件相对的一侧的电介质层上，其中第二级I / O连接被配置为将子模块连接到外部电路。 子模块的半导体器件附接到多层衬底结构的第一表面，其中介电材料位于介电层和多层衬底结构之间以填充表面安装结构中的间隙，并提供 额外的结构完整性。

公开(公告)号：US20140138806A1

公开(公告)日：2014-05-22

申请号：US14165707

申请日：2014-01-28

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L23/495 ,  H01L21/50 ,  H01L23/3735 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49811 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

Abstract translation: 公开了一种结合了引线框连接的功率覆盖（POL）封装结构。 该POL结构包括具有电介质层的POL子模块，附着到电介质层的至少一个半导体器件，并且包括由半导体材料构成的衬底和形成在衬底上的多个连接焊盘，以及金属互连 结构电耦合到所述至少一个半导体器件的多个连接焊盘，金属互连结构延伸穿过通过介电层形成的通孔，以便连接到多个连接焊盘。 POL结构还包括电耦合到POL子模块的引线框架，引线框架包括被配置为与外部电路结构互连的引线。