公开(公告)号：US20160118346A1

公开(公告)日：2016-04-28

申请号：US14893005

申请日：2013-05-20

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Mitsuaki Toda ,  Tohru Matsumoto ,  Ryoichi Shimizu

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/5384 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/2402 ,  H01L2224/24247 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/75745 ,  H01L2224/82001 ,  H01L2224/8201 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82986 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3641 ,  H05K1/188 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/40252 ,  H01L2924/40501 ,  H01L2924/403 ,  H01L2924/07802 ,  H01L2924/00014

Abstract: A device embedded substrate includes: an insulating layer; a first metal layer and a second metal layer that are formed such that the insulating layer is sandwiched therebetween; a device that is embedded in the insulating layer, and in which a connection terminal non-formation surface where a connection terminal is not formed is located on a side close to the first metal layer; an adhesive layer that is located on the connection terminal non-formation surface of the device; and a conductive via that electrically connects the second metal layer and the connection terminal of the device, wherein an area of the adhesive layer on a surface side in contact with the device is smaller than an area of the connection terminal non-formation surface of the device.

Abstract translation: 一种器件嵌入式衬底包括：绝缘层; 形成为使得绝缘层夹在其间的第一金属层和第二金属层; 嵌入在绝缘层中并且其中未形成连接端子的连接端子非形成表面的器件位于靠近第一金属层的一侧; 位于装置的连接端子非形成表面上的粘合剂层; 以及电连接所述第二金属层和所述装置的连接端子的导电孔，其中，与所述装置接触的表面侧的所述粘合剂层的面积小于所述装置的所述连接端子非形成面的面积 设备。

公开(公告)号：US06406939B1

公开(公告)日：2002-06-18

申请号：US09852822

申请日：2001-05-10

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L24/82 ,  H01L21/486 ,  H01L24/24 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/76155 ,  H01L2224/8201 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/83194 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A flip chip assembly, and methods of forming the same, including a single layer or multilayer substrate in which via holes serve as connections between a semiconductor chip and the substrate. The assembling steps comprise attaching a chip to a substrate having a plurality of via holes for connecting respective traces on the substrate with respective input/output terminal pads of the chip. The via holes are aligned with and placed on top of the pads so that the pads are exposed through the opposite side of the substrate. Electrically conductive material is subsequently deposited in the via holes as well as on the surface of the pads to provide electrical connections between the pads and the traces. Electrically conductive materials include electroless plated metals, electrochemical plated metals, solders, epoxies and conductive polymers.

Abstract translation: 倒装芯片组件及其形成方法，包括其中通孔用作半导体芯片和衬底之间的连接的单层或多层衬底。 组装步骤包括将芯片附接到具有多个通孔的衬底，用于将衬底上的各个迹线与芯片的相应输入/输出端子焊盘连接。 通孔与焊盘的顶部对齐并放置在焊盘的顶部，使得焊盘通过衬底的相对侧露出。 随后将导电材料沉积在通孔以及焊盘的表面上，以提供焊盘和迹线之间的电连接。 导电材料包括无电镀金属，电化学电镀金属，焊料，环氧树脂和导电聚合物。

公开(公告)号：US09936578B2

公开(公告)日：2018-04-03

申请号：US14517002

申请日：2014-10-17

Applicant: RF Micro Devices, Inc.

Inventor： Thong Dang ,  Mohsen Haji-Rahim ,  Mark Charles Held

IPC: H05K7/00 ,  H05K1/11 ,  H01L23/552 ,  H01L23/00 ,  H05K1/18 ,  H05K9/00 ,  H01L23/31 ,  H05K3/28

CPC classification number: H05K1/111 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/82136 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2924/1443 ,  H01L2924/1461 ,  H01L2924/15159 ,  H01L2924/15787 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/284 ,  H05K9/0022 ,  H05K2201/0715 ,  H05K2201/10439 ,  Y10T29/49016 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

Abstract: A shielded electronic module is formed on a substrate. The substrate has a component area and one or more electronic components attached to the component area. One set of conductive pads may be attached to the component area and another set of conductive pads may be provided on the electronic component. The conductive pads on the component area are electrically coupled to the conductive pads of the electronic component by a conductive layer. A first insulating layer is provided over the component area and underneath the conductive layer that may insulate the electronic component and the substrate from the conductive layer. A second insulating layer is provided over the first insulating layer that covers at least the conductive layer. In this manner, the conductive layer is isolated from an electromagnetic shield formed over the component area.

公开(公告)号：US20170317045A1

公开(公告)日：2017-11-02

申请号：US15481848

申请日：2017-04-07

Applicant: J-DEVICES CORPORATION

Inventor： Toshiyuki INAOKA ,  Atsuhiro URATSUJI

IPC: H01L23/00

CPC classification number: H01L24/27 ,  H01L24/04 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/64 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/03001 ,  H01L2224/03618 ,  H01L2224/03632 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15159 ,  H01L2224/83

Abstract: A manufacturing method of a semiconductor package includes locating, on a substrate, a semiconductor device having an external terminal provided on a top surface thereof, forming a resin insulating layer covering the semiconductor device, forming an opening, exposing the external terminal, in the resin insulating layer, performing plasma treatment on a bottom surface of the opening, performing chemical treatment on the bottom surface of the opening after the plasma treatment, and forming a conductive body to be connected with the external terminal exposed in the opening.

公开(公告)号：US20150371978A1

公开(公告)日：2015-12-24

申请号：US14418842

申请日：2013-07-19

Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

Inventor： Carlotta GUIDUCCI ,  Yusuf LEBLEBICI ,  Yüksel TEMIZ

IPC: H01L25/00 ,  G03F7/32 ,  G03F7/20 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/50 ,  G03F7/2022 ,  G03F7/32 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3185 ,  H01L24/02 ,  H01L24/05 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68381 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/27002 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82002 ,  H01L2224/82005 ,  H01L2224/8201 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/82143 ,  H01L2224/83143 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9205 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/00013 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method for performing a post processing pattern on a diced chip having a foot-print, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern.

Abstract translation: 一种用于在具有脚印的切割芯片上执行后处理图案的方法，包括以下步骤：提供支撑晶片; 将第一干膜光致抗蚀剂施加到所述支撑晶片; 将对应于切割的芯片的覆盖区的掩模定位在第一干膜光致抗蚀剂上; 将掩模和第一干膜光致抗蚀剂暴露于UV辐射; 取下面具; 光致抗蚀剂显影曝光的第一干膜光致抗蚀剂以获得与切割芯片相对应的空腔; 将切割的芯片定位在腔内; 将第二干膜光致抗蚀剂施加到第一膜光致抗蚀剂和切割的芯片上; 并且根据后处理图案曝光和显影施加到切割的芯片上的第二干膜光致抗蚀剂。

公开(公告)号：US20170164481A1

公开(公告)日：2017-06-08

申请号：US15039372

申请日：2014-10-09

Applicant: AT&S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT

Inventor： Johannes Stahr ,  Mike Morianz

IPC: H05K1/18 ,  H05K3/26 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/185 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/244 ,  H01L2224/2518 ,  H01L2224/8201 ,  H01L2224/82039 ,  H01L2224/82359 ,  H01L2224/82379 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/108 ,  H05K3/26 ,  H05K3/46 ,  H05K2201/09509 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2203/0392 ,  H05K2203/125

Abstract: A printed circuit board structure that includes at least one insulation layer, at least one conductor layer, and at least one embedded component having a contact pad that has an outer barrier layer, in which structure at least two conductor paths/conductor layers are connected to at least two connections using vias, and each via runs from a conductor path/conductor layer directly to the barrier contact layer of the corresponding connection of the component.

公开(公告)号：US20150084207A1

公开(公告)日：2015-03-26

申请号：US14037728

申请日：2013-09-26

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/522 ,  H01L23/42 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

公开(公告)号：US08716870B2

公开(公告)日：2014-05-06

申请号：US13328359

申请日：2011-12-16

Applicant: Arun Virupaksha Gowda

Inventor： Arun Virupaksha Gowda

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/24 ,  H01L23/3735 ,  H01L23/5389 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/82103 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device package having direct write interconnections and method of manufacturing thereof is disclosed. A device package is formed by providing a substrate structure, attaching at least one device to the substrate structure that each include a substrate and one or more connection pads formed on the substrate, depositing a dielectric layer over the at least one device and onto the substrate structure by way of a direct write application, the dielectric layer including vias formed therethrough, and forming an interconnect structure on the dielectric layer that is electrically coupled to the connection pads of the at least one device, the interconnect structure extending through the vias in the dielectric layer so as to be connected to the connection pads.

Abstract translation: 公开了一种具有直接写入互连的半导体器件封装及其制造方法。 通过提供衬底结构形成器件封装，将至少一个器件连接到衬底结构，每个器件包括衬底和形成在衬底上的一个或多个连接焊盘，在该至少一个器件上方沉积介电层并在衬底上 通过直接写入应用的结构，所述电介质层包括通过其形成的通孔，以及在电耦合到所述至少一个器件的连接焊盘的所述电介质层上形成互连结构，所述互连结构延伸穿过所述至少一个器件中的通孔 电介质层，以便连接到连接焊盘。

公开(公告)号：US09391027B2

公开(公告)日：2016-07-12

申请号：US14844515

申请日：2015-09-03

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/00 ,  H05K1/18 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H05K3/46 ,  H05K1/02 ,  H05K3/30 ,  H01L23/42 ,  H01L23/433

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

公开(公告)号：US20150380356A1

公开(公告)日：2015-12-31

申请号：US14844515

申请日：2015-09-03

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/538 ,  H01L23/528 ,  H05K1/18 ,  H01L23/367 ,  H01L23/373 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract translation: 封装结构包括介电层，至少一个连接到电介质层的半导体器件，一个或多个施加到电介质层的电介质片和半导体器件，以将半导体器件嵌入其中，并且多个 形成在形成在电介质层和一个或多个电介质层中的至少一个中的半导体器件上的通孔。 封装结构还包括形成在通孔中的金属互连和在封装结构的一个或多个向外表面上以形成与半导体器件的电互连的金属互连。 电介质层由在层压过程中不流动的材料组成，并且所述一个或多个电介质片中的每一个由可固化材料构成，所述可固化材料构造成在层压过程中固化时熔化和流动，以便填充任何空气 半导体器件周围的间隙。