公开(公告)号：US10403734B2

公开(公告)日：2019-09-03

申请号：US15656542

申请日：2017-07-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.

公开(公告)号：US10229999B2

公开(公告)日：2019-03-12

申请号：US15445392

申请日：2017-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Jiehui Shu

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

Abstract: A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure.

公开(公告)号：US10211315B2

公开(公告)日：2019-02-19

申请号：US15654165

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Haigou Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: Structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain region. A gate stack is deposited that coats the semiconductor fin and a contact landing area of the source/drain region adjacent to the semiconductor fin. The gate stack is patterned to remove the gate stack from the contact landing area and to form a gate electrode having a section adjacent to the contact landing area. The section of the gate electrode is laterally recessed to form a cavity, and a dielectric spacer is formed in the cavity.

公开(公告)号：US20190027575A1

公开(公告)日：2019-01-24

申请号：US15656542

申请日：2017-07-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Haigou Huang

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/762

CPC classification number: H01L29/518 ,  H01L21/76224 ,  H01L29/495 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/78 ,  H01L29/7831

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.

公开(公告)号：US10090169B1

公开(公告)日：2018-10-02

申请号：US15475272

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/321 ,  H01L29/49 ,  H01L21/3105

Abstract: The disclosure is directed to methods of forming an integrated circuit structure. One method may include: forming a metal gate within a dielectric layer over a substrate; forming an opening within the metal gate; recessing the metal gate such that a height of the metal gate is reduced; forming an insulator over the recessed metal gate and filling the opening; and planarizing the insulator to a top surface of the dielectric layer.

公开(公告)号：US10062772B2

公开(公告)日：2018-08-28

申请号：US15219370

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Xusheng Wu ,  Xintuo Dai

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L29/66795 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure.

公开(公告)号：US09991361B2

公开(公告)日：2018-06-05

申请号：US15165294

申请日：2016-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Haigou Huang ,  Xusheng Wu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer is formed above the first hard mask layer. The second hard mask layer is patterned to define an opening therein exposing a portion of the first hard mask layer and being disposed above a portion of the placeholder gate structure. The exposed portion of the first hard mask layer and the portion of the sacrificial material of the placeholder gate structure disposed below the opening are removed to define a gate cut cavity and divide the placeholder gate structure into first and second segments. A dielectric material is formed in the gate cut cavity.

公开(公告)号：US09966272B1

公开(公告)日：2018-05-08

申请号：US15632931

申请日：2017-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haifeng Sheng ,  Haigou Huang ,  Tai Fong Chao ,  Jiehui Shu ,  Jinping Liu ,  Xingzhao Shi ,  Laertis Economikos

IPC: H01L21/00 ,  H01L21/3105

CPC classification number: H01L21/31056 ,  H01L21/31055 ,  H01L21/762 ,  H01L21/823878

Abstract: The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.

公开(公告)号：US09922972B1

公开(公告)日：2018-03-20

申请号：US15491222

申请日：2017-04-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaofeng Qiu ,  Haigou Huang ,  Chang Ho Maeng

IPC: H01L21/461 ,  H01L23/12 ,  H01L23/043 ,  H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823475

Abstract: A lithography method and accompanying structure for decreasing the critical dimension (CD) and improving the CD uniformity within semiconductor devices uses a layer of silicon carbide as an embedded blocking mask for defining semiconductor architectures, including contact trench openings to form trench silicide contacts.

公开(公告)号：US09911736B1

公开(公告)日：2018-03-06

申请号：US15622949

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang ,  Xiaofeng Qiu

IPC: H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/31053 ,  H01L21/28123 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.