公开(公告)号：US09263338B2

公开(公告)日：2016-02-16

申请号：US14060874

申请日：2013-10-23

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。

公开(公告)号：US09236258B2

公开(公告)日：2016-01-12

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。

公开(公告)号：US20150380510A1

公开(公告)日：2015-12-31

申请号：US14849483

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai

IPC: H01L29/45 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/456 ,  H01L21/02634 ,  H01L21/28518 ,  H01L21/76886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention provide a semiconductor structure and a method of forming a semiconductor structure. Embodiments of the semiconductor structure have a plurality of fins on a substrate. The semiconductor has, and the method achieves, a silicide layer formed on and substantially surrounding at least one epitaxial region formed on a top portion of the plurality of fins. Embodiments of the present invention provide a method and structure for forming a conformal silicide layer on the epitaxial regions that are formed on the top portion of unmerged fins of a finFET.

公开(公告)号：US20150372107A1

公开(公告)日：2015-12-24

申请号：US14308014

申请日：2014-06-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31111 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures associated with forming finFETs that have fin pitches less than 30 nm are described. A selective nitridation process may be used during spacer formation on the gate to enable finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.

Abstract translation: 描述了与形成翅片间距小于30nm的finFET相关联的方法和结构。 可以在栅极上的间隔物形成期间使用选择性氮化工艺，以使得能够使用传统间隔物沉积工艺可以获得更细的翅片间距。 间隔物形成还可以允许对源极和漏极结的形成的精确控制。

公开(公告)号：US20150364578A1

公开(公告)日：2015-12-17

申请号：US14307011

申请日：2014-06-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai ,  Kejia Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/66795 ,  H01L29/20 ,  H01L29/205 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.

Abstract translation: 描述了形成finFET的电阻减小区域的方法和结构。 根据一些方面，可以在包括第一半导体组合物的鳍片之上形成伪栅极和第一栅极间隔物。 可以去除鳍的源区和漏区的至少一部分，并且可以在与第一半导体组合物接触的源区和漏区中形成第二半导体组合物。 可以形成覆盖第一栅极间隔物的第二栅极间隔物。 该方法可用于形成在源极和漏极结处具有降低的电阻的finFET。

公开(公告)号：US09214553B2

公开(公告)日：2015-12-15

申请号：US14200952

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 所公开的一种方法包括形成由衬底，第一外延半导体材料和第二外延半导体材料的部分组成的初始鳍结构，形成绝缘材料层，从而过度填充限定 翅片，使一层绝缘材料凹陷，使得最终翅片结构的第二外延半导体部分的一部分（但不是全部）暴露，围绕最终翅片结构形成栅极结构，进一步使绝缘材料层凹陷，使得 第一外延半导体材料被暴露，去除第一外延半导体材料，从而限定下鳍腔，并用受压材料基本上填充底鳍腔。

公开(公告)号：US20150357441A1

公开(公告)日：2015-12-10

申请号：US14300506

申请日：2014-06-10

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片，以及覆盖半导体鳍片的栅极。 门具有锥形外表面。 在栅极附近形成第一对侧壁间隔物，露出的锥形外表面也被限定。 在露出的锥形外表面上去除栅极的部分以限定凹部。 形成第二对侧壁间隔件，覆盖第一对侧壁间隔件和凹部。 源极/漏极区域形成在半导体鳍片上。

公开(公告)号：US20150357425A1

公开(公告)日：2015-12-10

申请号：US14297822

申请日：2014-06-06

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US09202919B1

公开(公告)日：2015-12-01

申请号：US14447685

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

Abstract: Techniques and structures for shaping the source and drain junction profiles of a finFET are described. A fin may be partially recessed at the source and drain regions of the finFET. The partially recessed fin may be further recessed laterally and vertically, such that the laterally recessed portion extends under at least a portion of the finFET's gate structure. Source and drain regions of the finFET may be formed by growing a buffer layer on the etched surfaces of the fin and/or growing a source and drain layer at the source and drain regions of the fin. The lateral recess can improve channel-length uniformity along the height of the fin.

Abstract translation: 描述了用于成形finFET的源极和漏极结线廓的技术和结构。 翅片可以部分地凹陷在finFET的源极和漏极区域。 部分凹入的翅片可以进一步侧向和垂直地凹入，使得横向凹入部分在finFET的栅极结构的至少一部分下方延伸。 可以通过在鳍的蚀刻表面上生长缓冲层和/或在鳍的源极和漏极区生长源极和漏极层来形成鳍FET的源区和漏极区。 横向凹槽可以改善沿翅片高度的通道长度均匀性。

公开(公告)号：US20150311081A1

公开(公告)日：2015-10-29

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。