公开(公告)号：US20220037348A1

公开(公告)日：2022-02-03

申请号：US16940522

申请日：2020-07-28

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yongshun Sun ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L27/11568 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L23/535

Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells.

公开(公告)号：US11211550B2

公开(公告)日：2021-12-28

申请号：US16939105

申请日：2020-07-27

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Samarth Agarwal ,  Ruchil Kumar Jain ,  Kiok Boone Elgin Quek

IPC: G11C11/00 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12

Abstract: In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.

公开(公告)号：US11047930B2

公开(公告)日：2021-06-29

申请号：US16297880

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yongshun Sun ,  Eng Huat Toh ,  Kiok Boone Elgin Quek

IPC: H01L43/06 ,  G01R33/00 ,  H01L43/14 ,  H01L27/22 ,  G01R33/07 ,  H01L43/04

Abstract: A device having a Hall effect sensor is provided. The Hall effect sensor includes a sensor well and a Hall plate disposed within the sensor well. The Hall plate includes a first current terminal and a second current terminal configured to flow a current through the Hall plate, and the Hall plate further includes a first sensing terminal and a second sensing terminal configured to sense a Hall voltage. A separation layer and a separation well are disposed within the sensor well, as well as surround the Hall plate and isolate the Hall plate. At least one of a current sensitivity and a resistance of the Hall effect sensor is tunable based on an adjustable thickness of the Hall plate. The thickness of the Hall plate is adjustable based at least in part on implants in the separation layer and/or a bias voltage applied to the separation layer.

公开(公告)号：US20200135275A1

公开(公告)日：2020-04-30

申请号：US16174318

申请日：2018-10-30

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: G11C16/10 ,  H01L27/11521 ,  G11C16/04 ,  G11C16/14

Abstract: A device having at least one memory cell over a substrate is provided. The at least one memory cell includes a source region and a drain region in the substrate, and a first gate and a second gate over the substrate. The first and second gates are arranged between the source region and the drain region. The first and second gate are separated by an intergate dielectric. The first gate is configured as a select gate and erase gate of the at least one memory cell, and the second gate is configured as a storage gate of the at least one memory cell. The second gate comprises a floating gate and a control gate over the floating gate. The device further includes source/drain (S/D) contacts extending from the source region and the drain region. The source region and the drain region are coupled to either one of a source line (SL) or a bit line (BL) through the S/D contacts.

公开(公告)号：US20200098822A1

公开(公告)日：2020-03-26

申请号：US16138363

申请日：2018-09-21

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Bin Liu ,  Kiok Boone Elgin Quek

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetoresistive random access memory (MRAM) structures and arrays, methods for fabricating MRAM structures and arrays, and methods for operating MRAM structures and arrays are provided. An exemplary MRAM structure includes an access transistor having a source and a drain, a first magnetic tunnel junction (MTJ) element coupled to the source of the access transistor, and a second magnetic tunnel junction (MTJ) element coupled to the drain of the access transistor.

公开(公告)号：US10580781B2

公开(公告)日：2020-03-03

申请号：US15730742

申请日：2017-10-12

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng Tan ,  Kiok Boone Elgin Quek ,  Eng Huat Toh

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L29/10 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/28 ,  H01L27/1159 ,  H01L27/11558 ,  H01L27/11524

Abstract: Devices and methods of forming a device are disclosed. The device includes a substrate defined with at least a device region. A multi-gate transistor disposed in the device region which includes first and second gates both having first and second gate sidewalls. The multi-gate transistor also includes first source/drain (S/D) regions disposed adjacent to the first gate sidewall of the first and second gate, a common second S/D region disposed adjacent to the second gate sidewall of the first and second gate. A negative capacitance element is disposed within the second gate to reduce total overlap capacitance of the transistor. An interlevel dielectric (ILD) layer is disposed over the substrate and covering the transistor. First and second contacts are disposed in the ILD layer which are coupled to the first and second S/D regions respectively.

公开(公告)号：US10205000B2

公开(公告)日：2019-02-12

申请号：US14981980

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xueming Dexter Tan ,  Kiok Boone Elgin Quek ,  Xinfu Liu

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/167

Abstract: A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

公开(公告)号：US10134459B2

公开(公告)日：2018-11-20

申请号：US15012763

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Vinayak Bharat Naik ,  Chenchen Jacob Wang ,  Kiok Boone Elgin Quek

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.

公开(公告)号：US20180083008A1

公开(公告)日：2018-03-22

申请号：US15267664

申请日：2016-09-16

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Pengfei Guo ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L27/105 ,  H01L27/092 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L49/02 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L29/66681 ,  H01L27/11558 ,  H01L28/40 ,  H01L29/7835 ,  H01L29/7885

Abstract: Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an embodiment, an MTP memory cell includes a semiconductor substrate including a CMOS device region and a DMOS device region. The MTP memory cell further includes a high voltage (HV) p-well in the CMOS device region and in the DMOS device region of the semiconductor substrate. An n-channel transistor is disposed over the HV p-well in the CMOS device region and includes a transistor gate. Also, the MTP memory cell includes an n-well overlying the HV p-well in the DMOS region of the semiconductor substrate. An n-channel capacitor is disposed over the n-well and includes a capacitor gate. The capacitor gate is coupled to the transistor gate.

公开(公告)号：US09871076B2

公开(公告)日：2018-01-16

申请号：US15091551

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Xuan Anh Tran ,  Kiok Boone Elgin Quek

IPC: H01L27/22 ,  H01L29/66 ,  H01L43/12 ,  H01L21/02 ,  H01L21/768 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L23/528

CPC classification number: H01L27/226 ,  G11C11/161 ,  H01L21/0257 ,  H01L21/02636 ,  H01L21/768 ,  H01L23/528 ,  H01L28/00 ,  H01L29/66234 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate with a cell region. Selector units and storage units are formed within the substrate. The selector unit includes first and second bipolar junction transistors (BJTs). The selector unit includes first and second bipolar junction transistors (BJTs). A BJT includes first, second and third BJT terminals. The second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal. The third BJT terminal of the first BJT serves as a first bitline terminal, and the third BJT terminal of the second BJT serves as a second bitline terminal. A storage unit is disposed over the selector unit. The storage unit includes a first pinning layer which is coupled to the first BJT terminal of the first BJT, a second pinning layer which is coupled to the first BJT terminal of the second BJT, a free layer which includes an elongated member with first and second major surfaces and first and second end regions separated by a free region. The first pinning layer is coupled to the second major surface of the free layer in the first end region and the second pinning layer is coupled to the second major surface of the free layer in the second end region. A reference stack is disposed on the first major surface of the free layer in the free region. The reference stack serves as a read bitline terminal.