公开(公告)号：US08054279B2

公开(公告)日：2011-11-08

申请号：US11853090

申请日：2007-09-11

申请人： Atsushi Umezaki ,  Hiroyuki Miyake

发明人： Atsushi Umezaki ,  Hiroyuki Miyake

IPC分类号： G09G3/36

CPC分类号： H01L27/124 ,  G09G3/2092 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/061 ,  G09G2320/0646 ,  G09G2320/0666 ,  G11C19/28 ,  H01L27/0207 ,  H01L27/1222 ,  H01L27/1225

摘要： To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

摘要翻译： 为了抑制晶体管的阈值电压的波动，为了减少显示面板和驱动器IC的连接数量，为了实现显示装置的功耗的降低，并且实现显示装置的尺寸和高清晰度的增加 。 容易恶化的晶体管的栅电极通过第一开关晶体管和通过第二开关晶体管供给低电位的布线而连接到提供高电位的布线; 时钟信号被输入到第一开关晶体管的栅电极; 并且反相时钟信号被输入到第二开关晶体管的栅电极。 因此，高电位和低电位交替施加到容易劣化的晶体管的栅电极。

公开(公告)号：US20110260169A1

公开(公告)日：2011-10-27

申请号：US13174895

申请日：2011-07-01

申请人： Atsushi Umezaki ,  Hiroyuki Miyake

发明人： Atsushi Umezaki ,  Hiroyuki Miyake

IPC分类号： H01L33/08

CPC分类号： G02F1/1368 ,  G02F1/136286 ,  G09G3/20 ,  G09G3/2022 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/342 ,  G09G3/3426 ,  G09G3/3677 ,  G09G3/3685 ,  G09G2300/043 ,  G09G2300/0852 ,  G09G2310/0248 ,  G09G2310/0262 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/0297 ,  G09G2320/0233 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2352/00 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/156 ,  H01L27/3232 ,  H01L27/3276 ,  H01L29/42384 ,  H01L2924/0002 ,  H01L2924/00

摘要： An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

摘要翻译： 本发明的目的是提供一种能够降低显示装置的功耗和高清晰度的电路技术。 将由启动信号控制的开关提供给晶体管的栅电极，该晶体管连接到自举晶体管的栅电极。 当输入起始信号时，通过开关将电位提供给晶体管的栅电极，晶体管截止。 晶体管截止，从而可以防止电荷从自举晶体管的栅电极泄漏。 因此，可以缩短在自举晶体管的栅电极中存储电荷的时间，并且可以执行高速操作。

公开(公告)号：US20110254816A1

公开(公告)日：2011-10-20

申请号：US13084030

申请日：2011-04-11

申请人： Atsushi Umezaki

发明人： Atsushi Umezaki

IPC分类号： G09G5/00

CPC分类号： G09G3/344 ,  G09G3/3433 ,  G09G2300/08 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/0272

摘要： A display device comprising a display area in which a plurality of pixels, a plurality of gate signal lines, and a plurality of source signal lines are arranged in a matrix; a scan line driver circuit having a function of controlling a timing of selecting any one of the plurality of gate signal lines; and a signal line driver circuit having a function of controlling, in a period during which the scan line driver circuit selects any one of the plurality of gate signal lines, a timing of outputting a first signal to all the plurality of source signal lines and then outputting a second signal to any one of the plurality of source signal lines. Each of the plurality of pixels includes a transistor and a display element being sandwiched between a pixel electrode and a common electrode and having memory properties.

摘要翻译： 一种显示装置，包括：多个像素，多个栅极信号线和多个源极信号线排列成矩阵的显示区域; 扫描线驱动电路，其具有控制选择所述多个栅极信号线中的任一个的定时的功能; 以及信号线驱动电路，具有在扫描线驱动电路选择多个栅极信号线中的任一个的期间，控制对所有多个源极信号线输出第一信号的定时，然后 向所述多个源信号线中的任一个输出第二信号。 多个像素中的每一个包括晶体管和显示元件，其夹在像素电极和公共电极之间并具有记忆特性。

公开(公告)号：US07687808B2

公开(公告)日：2010-03-30

申请号：US11863913

申请日：2007-09-28

申请人： Atsushi Umezaki

发明人： Atsushi Umezaki

IPC分类号： G09G3/36

CPC分类号： H01L27/124 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2202/103 ,  G09G3/3266 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/023 ,  G11C19/28 ,  H01L27/105 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/42384 ,  H01L29/78663 ,  H01L29/78678 ,  H01L29/78696

摘要： By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

摘要翻译： 通过将AC脉冲施加到容易劣化的晶体管的栅极，抑制了晶体管的阈值电压偏移。 然而，在非晶硅用于晶体管的半导体层的情况下，阈值电压偏移的发生自然成为构成产生AC脉冲的电路的一部分的晶体管的问题。 容易劣化的晶体管的阈值电压偏移和导通晶体管的阈值电压偏移被信号输入到通过导通晶体管容易劣化的晶体管的栅电极而被抑制。 换句话说，包括将AC脉冲施加到通过晶体管容易劣化到施加了高电位（VDD）的栅电极的晶体管的栅电极的结构。

公开(公告)号：US09153341B2

公开(公告)日：2015-10-06

申请号：US11539429

申请日：2006-10-06

申请人： Atsushi Umezaki

发明人： Atsushi Umezaki

IPC分类号： G09G3/36 ,  G11C19/18 ,  G09G3/32

CPC分类号： G11C19/184 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2320/02 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/023

摘要： The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire.

摘要翻译： 本发明提供一种半导体器件和移位寄存器，其中在非选择期间引起低噪声，并且晶体管不总是导通。 提供第一至第四晶体管。 第一晶体管的源极和漏极之一连接到第一线，源极和漏极中的另一个连接到第二晶体管的栅电极，并且其栅电极连接到第五线。 第二晶体管的源极和漏极之一连接到第三导线，并且源极和漏极中的另一个连接到第六导线。 第三晶体管的源极和漏极之一连接到第二导线，源极和漏极中的另一个连接到第二晶体管的栅电极，并且其栅电极连接到第四线。 第四晶体管的源极和漏极之一连接到第二线，源极和漏极的另一个连接到第六线，并且其栅电极连接到第四线。

公开(公告)号：US08836686B2

公开(公告)日：2014-09-16

申请号：US13044130

申请日：2011-03-09

申请人： Atsushi Umezaki ,  Hiroyuki Miyake

发明人： Atsushi Umezaki ,  Hiroyuki Miyake

IPC分类号： G09G5/00

CPC分类号： G09G3/006 ,  G09G3/3648 ,  G09G2310/04 ,  G09G2320/046 ,  G11C19/28

摘要： To provide a display device in which rewriting of only a given section of an image can be achieved or to simplify the configuration of a circuit including wirings in a display device in which partial driving can be performed. A shift of a selection signal in a shift register included in a scan line driver circuit and supply of a selection signal to scan lines are controlled independently of each other, so that rewriting of only a given section of an image can be achieved. The above operation is realized by providing a wiring that supplies a signal representing a clock signal or a fixed potential. Therefore, the configuration of the circuit including the wiring can be simplified in the display device including the wiring while partial driving can be performed.

摘要翻译： 为了提供一种显示装置，其中仅可以实现图像的给定部分的重写，或者简化包括能够执行部分驱动的显示装置中的布线的电路的配置。 包括在扫描线驱动器电路中的移位寄存器中的选择信号的移位和对扫描线的选择信号的提供彼此独立地被控制，使得仅可以实现图像的给定部分的重写。 通过提供提供表示时钟信号或固定电位的信号的布线来实现上述操作。 因此，可以在包括布线的显示装置中简化包括布线的电路的构造，同时可以进行部分驱动。

公开(公告)号：US08736315B2

公开(公告)日：2014-05-27

申请号：US13606440

申请日：2012-09-07

申请人： Atsushi Umezaki

发明人： Atsushi Umezaki

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H01L27/1255 ,  G09G3/14 ,  G09G3/32 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00 ,  H01L29/7869 ,  H03B1/00 ,  H03K3/00 ,  H03K17/6871

摘要： Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

摘要翻译： 提供一种半导体器件，其特征在于晶体管数量减少的逆变器电路和移位寄存器电路。 半导体器件包括第一晶体管，第二晶体管和电容器。 第一晶体管的源极和漏极之一电连接到第一布线，另一个电连接到第二布线。 第二晶体管的源极和漏极之一电连接到第一布线，第二晶体管的栅极电连接到第一晶体管的栅极，第二晶体管的源极和漏极的另一个是 电连接到电容器的一个电极，而电容器的另一个电极电连接到第三布线。 第一和第二晶体管具有相同的导电类型。

公开(公告)号：US08698852B2

公开(公告)日：2014-04-15

申请号：US13105312

申请日：2011-05-11

申请人： Atsushi Umezaki

发明人： Atsushi Umezaki

IPC分类号： G09G5/10

CPC分类号： G09G3/344 ,  G09G2300/0482 ,  G09G2310/06 ,  G09G2330/021 ,  G09G2330/022

摘要： A method for driving a display device including pixels each including a display element and a transistor is proposed. The driving method has an image production period and an image retention period. In the image production period, a video signal is input to each pixel and the gray level of the display element in each pixel is controlled in accordance with the video signal so that an image is produced. In the image retention period, a retention signal is input to each pixel and the gray level of the display element in each pixel is held so that the image produced in the image production period is retained. Deterioration of the transistor can be suppressed by making the absolute value of the potential difference between the gate and the second terminal of the transistor smaller in the image retention period than in the image production period.

摘要翻译： 提出了一种用于驱动包括各自包括显示元件和晶体管的像素的显示装置的方法。 驱动方法具有图像生成期间和图像保持期间。 在图像生成期间，向每个像素输入视频信号，并且根据视频信号控制每个像素中的显示元素的灰度级，从而产生图像。 在图像保持期间，保持信号被输入到每个像素，并且保持每个像素中的显示元素的灰度级，从而保持在图像生成期间中产生的图像。 通过使晶体管的栅极和第二端子之间的电位差的绝对值在图像保持期间比在图像生成期间更小，可以抑制晶体管的劣化。

公开(公告)号：US08638322B2

公开(公告)日：2014-01-28

申请号：US13014026

申请日：2011-01-26

申请人： Atsushi Umezaki

发明人： Atsushi Umezaki

IPC分类号： G09G5/00

CPC分类号： G09G3/3611 ,  G09G3/3659 ,  G09G2300/0439 ,  G09G2300/0814

摘要： A display device in which partial driving can be performed with a simplified configuration of a circuit including a wiring. One of signal processing circuits includes a first transistor that controls the potential of its respective gate signal line, and a second transistor that outputs a start signal for the subsequent stage and a reset signal for the preceding stage. A signal for controlling whether the gate signal line is in an active state (a state where a selection signal is output) or a non-active state (a state where a selection signal is not output or a non-selection signal continues to be output) is input to the first transistor. A clock signal is input to the second transistor. Thus, the number of wirings necessary for operating the device is reduced.

摘要翻译： 可以以包括布线​​的电路的简化配置来执行部分驱动的显示装置。 信号处理电路中的一个包括控制其各自的栅极信号线的电位的第一晶体管和输出后级的起始信号的第二晶体管和用于前一级的复位信号。 用于控制栅极信号线是否处于有效状态（选择信号被输出的状态）还是非有效状态（选择信号不输出的状态或者非选择信号继续输出的信号）的信号 ）被输入到第一晶体管。 时钟信号被输入到第二晶体管。 因此，减少了操作装置所需的布线数量。

公开(公告)号：US08619104B2

公开(公告)日：2013-12-31

申请号：US13021215

申请日：2011-02-04

申请人： Atsushi Umezaki ,  Hiroyuki Miyake

发明人： Atsushi Umezaki ,  Hiroyuki Miyake

IPC分类号： G09G5/10

CPC分类号： G09G3/3648 ,  G02F1/1368 ,  G09G2300/0426 ,  G09G2300/0876 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2330/021 ,  G09G2340/0435

摘要： It is an object to suppress deterioration of a displayed still image which is caused when a refresh rate is reduced. A liquid crystal display device includes a display portion controlled by a driver circuit and a timing controller for controlling the driver circuit. An image signal for displaying a still image is supplied to the timing controller. By the timing controller, a refresh rate in displaying an image corresponding to an image signal on the display portion reduced as a gray level number of the image signal is smaller.

摘要翻译： 本发明的目的是抑制刷新率降低时所显示的静止图像的劣化。 液晶显示装置包括由驱动电路控制的显示部分和用于控制驱动电路的定时控制器。 用于显示静止图像的图像信号被提供给定时控制器。 通过定时控制器，显示与图像信号的灰度级数减少的显示部分上的图像信号相对应的图像的刷新率较小。