公开(公告)号：US10777444B2

公开(公告)日：2020-09-15

申请号：US15951213

申请日：2018-04-12

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Gerald Lackner ,  Josef Unterweger

IPC: B65D85/02 ,  H01L21/683 ,  H01L21/304 ,  H01L21/673

Abstract: A wafer arrangement in accordance with various embodiments may include: a wafer; and a wafer support ring, wherein the wafer and the wafer support ring are configured to be releasably coupled to one another so that the wafer support ring can be uncoupled from the wafer without causing damage to the wafer or the wafer support ring.

公开(公告)号：US10749216B2

公开(公告)日：2020-08-18

申请号：US14230056

申请日：2014-03-31

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Alexander Breymesser ,  Bernhard Goller ,  Kamil Karlovsky ,  Francisco Javier Santos Rodriguez ,  Peter Zorn

IPC: H01L23/58 ,  H01M10/42 ,  H01M10/0585 ,  H01M10/052 ,  H01M2/02

Abstract: A battery includes a first substrate having a first main surface, a second substrate made of a conducting material or semiconductor material, and a carrier of an insulating material. The carrier has a first and a second main surfaces, the second substrate being attached to the first main surface of the carrier. An opening is formed in the second main surface of the carrier to uncover a portion of a second main surface of the second substrate. The second main surface of the carrier is attached to the first substrate, thereby forming a cavity. The battery further includes an electrolyte disposed in the cavity.

公开(公告)号：US10699934B2

公开(公告)日：2020-06-30

申请号：US14872184

申请日：2015-10-01

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Roland Rupp ,  Ronny Kern ,  Josef Unterweger

IPC: H01L21/683

Abstract: According to various embodiments, a substrate carrier may include: a substrate-supporting region for supporting a substrate; wherein a first portion of the substrate-supporting region including a pore network of at least partially interconnected pores; wherein a second portion of the substrate-supporting region surrounds the first portion and includes a sealing member for providing a contact sealing; at least one evacuation port for creating a vacuum in the pore network, such that a substrate received over the substrate-supporting region is adhered by suction; and at least one valve configured to control a connection between the pore network and the at least one evacuation port, such that a vacuum can be maintained in the pore network; wherein the pore network includes a first pore characteristic in a first region and a second pore characteristic in a second region different from the first pore characteristic.

公开(公告)号：US20200176580A1

公开(公告)日：2020-06-04

申请号：US16693909

申请日：2019-11-25

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Iris Moder ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Carsten von Koblinski

IPC: H01L29/49 ,  H01L29/16 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02 ,  H01L21/04 ,  H01L29/66

Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.

公开(公告)号：US20200161269A1

公开(公告)日：2020-05-21

申请号：US16685318

申请日：2019-11-15

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Fabian Craes ,  Barbara Eichinger ,  Martin Mischitz ,  Frederik Otto ,  Fabien Thion

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/428

Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.

公开(公告)号：US20190337069A1

公开(公告)日：2019-11-07

申请号：US15971830

申请日：2018-05-04

Applicant: Infineon Technologies AG

Inventor： Nirdesh Ojha ,  Francisco Javier Santos Rodriguez ,  Roland Rupp ,  Markus Heinrici ,  Karin Delalut ,  Claudia Friza

IPC: B23H7/06 ,  B23H7/10 ,  B23H7/14 ,  B23H7/30 ,  B23H7/34 ,  B23H1/02

Abstract: A method of yielding a thinner product wafer from a thicker base SiC wafer cut from a SiC ingot includes: supporting the base SiC wafer with a support substrate: and while the base SiC wafer is supported by the support substrate, cutting through the base SiC wafer in a direction parallel to a first main surface of the base SiC wafer using a wire as part of a wire electrical discharge machining (WEDM) process, to separate the product wafer from the base SiC wafer, the product wafer being attached to the support substrate when cut from the base SiC wafer.

公开(公告)号：US10461056B2

公开(公告)日：2019-10-29

申请号：US15600857

申请日：2017-05-22

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L23/495

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

公开(公告)号：US20190123185A1

公开(公告)日：2019-04-25

申请号：US16167926

申请日：2018-10-23

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Markus Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Alexander Philippou ,  Francisco Javier Santos Rodriguez

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L21/225 ,  H01L21/324 ,  H01L21/265 ,  H01L29/423 ,  H01L21/033

Abstract: A method of processing a semiconductor device includes: providing a semiconductor body with a drift region; forming trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement having a lateral structure so that some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; subjecting the semiconductor body and the mask arrangement to a dopant material providing step to form a plurality of doping regions of a second conductivity type below bottoms of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step so that the doping regions extend in parallel to the first lateral direction and overlap to form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

公开(公告)号：US10049914B2

公开(公告)日：2018-08-14

申请号：US14946886

申请日：2015-11-20

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Hans-Joachim Schulze ,  Francisco Javier Santos Rodriguez ,  Iris Moder ,  Ingo Muri

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

Abstract: According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.

公开(公告)号：US10049912B2

公开(公告)日：2018-08-14

申请号：US15424118

申请日：2017-02-03

Applicant: Infineon Technologies AG

Inventor： Alexander Breymesser ,  Andre Brockmeier ,  Elmar Falck ,  Francisco Javier Santos Rodriguez ,  Holger Schulze

IPC: H01L21/762 ,  H01L21/78 ,  H01L29/78 ,  H01L29/06 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame trench, an edge termination structure comprising a glass structure, forming a conductive layer on the semiconductor substrate and the edge termination structure, and removing a portion of the conductive layer above the edge termination structure. A remnant portion of the conductive layer forms a conductive structure that covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench.