公开(公告)号：US20190097057A1

公开(公告)日：2019-03-28

申请号：US16203780

申请日：2018-11-29

Applicant: Intel Corporation

Inventor： Neville L. Dias ,  Chia-Hong Jan ,  Walid M. Hafez ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu

IPC: H01L29/78 ,  H01L21/8234 ,  H03D7/16

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

公开(公告)号：US10229853B2

公开(公告)日：2019-03-12

申请号：US14914179

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H01L21/84 ,  H01L29/66

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US10158034B2

公开(公告)日：2018-12-18

申请号：US15127207

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Nidhi Nidhi ,  Chia-Hong Jan ,  Walid M. Hafez ,  Yi Wei Chen

IPC: H01L31/044 ,  H01L31/0224 ,  H01L31/056 ,  H01L31/047 ,  H02S40/38 ,  H01L31/028 ,  H01L31/05 ,  H01L31/068 ,  H01L31/18

Abstract: An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.

公开(公告)号：US10096599B2

公开(公告)日：2018-10-09

申请号：US14977367

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Curtis Tsai ,  Chia-Hong Jan ,  Jeng-Ya David Yeh ,  Joodong Park ,  Walid M. Hafez

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/51

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

公开(公告)号：US09881927B2

公开(公告)日：2018-01-30

申请号：US14780222

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Walid M. Hafez ,  Joodong Park

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/112 ,  H01L29/66 ,  H01L23/525 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/11206 ,  H01L21/823431 ,  H01L23/5256 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode.

公开(公告)号：US09786783B2

公开(公告)日：2017-10-10

申请号：US13995717

申请日：2013-03-29

Applicant: INTEL CORPORATION

Inventor： Walid M. Hafez ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Curtis Tsai

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78

Abstract: Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (Lb) and a simultaneous increase in threshold voltage (VT). The disclosed techniques can be implemented with planar and non-planar fin-based architectures and can be used in standard metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) process flows, in some embodiments.

公开(公告)号：US09748327B2

公开(公告)日：2017-08-29

申请号：US15129794

申请日：2014-06-18

Applicant: INTEL CORPORATION

Inventor： Chen-Guan Lee ,  Walid Hafez ,  Chia-Hong Jan

IPC: G11C11/00 ,  H01L45/00 ,  H01L49/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/66

CPC classification number: H01L28/20 ,  H01L21/8234 ,  H01L23/66 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/24 ,  H01L29/785

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

公开(公告)号：US20170092726A1

公开(公告)日：2017-03-30

申请号：US15126812

申请日：2014-06-18

Applicant: INTEL CORPORATION

Inventor： Nidhi Nidhi ,  Chia-Hong Jan ,  Walid M. Hafez

IPC: H01L29/40 ,  H01L23/66 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/402 ,  H01L21/26513 ,  H01L23/66 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/404 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection. In an embodiment, a deep well implant may be disposed between a lightly-doped extended-drain and a substrate to reduce drain-body junction capacitance and improve transistor performance.

公开(公告)号：US09356023B2

公开(公告)日：2016-05-31

申请号：US13995755

申请日：2013-03-30

Applicant: INTEL CORPORATION

Inventor： Walid M. Hafez ,  Peter J. Vandervoorn ,  Chia-Hong Jan

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/1608 ,  H01L29/161

Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.

Abstract translation: 公开了在finFET制造工艺流程期间在基于鳍片的场效应晶体管（finFET）架构上形成平面状晶体管器件的技术。 在一些实施例中，平面状晶体管可以包括例如半导体层，该半导体层被生长以局部地合并/桥接finFET架构的多个相邻鳍片，并且随后被平坦化以提供高质量的平面表面，平面 形晶体管。 在一些情况下，半导体合并层可以是桥接外延生长，例如包括外延硅。 在一些实施例中，这样的平面状器件可以辅助例如模拟，高电压，宽Z晶体管制造。 此外，在finFET流动期间提供这样的平面状器件可以允许形成晶体管器件，例如，显示出更低的电容，更宽的Z和/或更少的高电场位置，以改善高电压可靠性，其可以 在某些情况下，使这种设备有利于模拟设计。

公开(公告)号：US11881486B2

公开(公告)日：2024-01-23

申请号：US18111313

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/1211 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.