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公开(公告)号：US20180301110A1
公开(公告)日：2018-10-18
申请号：US15488561
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Louis Feng , Altug Koker , Tomasz Janczak , Andrew T. Lauritzen , David M. Cimini , Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws , Devan Burke , Elmoustapha Ould-Ahmed-Vall , Abhishek R. Appu
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
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公开(公告)号：US20180300096A1
公开(公告)日：2018-10-18
申请号：US15488758
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Eric J. Asperheim , Subramaniam M. Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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公开(公告)号：US20180293698A1
公开(公告)日：2018-10-11
申请号：US15483641
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Abhishek Venkatesh , Prasoonkumar Surti , Slawomir Grajewski , Louis Feng , Kai Xiao , Tomasz Janczak , Devan Burke , Travis T. Schluessler
Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.
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公开(公告)号：US20180286105A1
公开(公告)日：2018-10-04
申请号：US15477019
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer KP , Jonathan Kennedy , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Tomer Bar-On , Carsten Benthin , Adam T. Lake , Vasanth Ranganathan , Abhishek R. Appu
CPC classification number: H04N5/23212 , G02B27/017 , G06K9/00765 , G06T15/005 , H04N13/239 , H04N13/344
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
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公开(公告)号：US09940904B2
公开(公告)日：2018-04-10
申请号：US14061174
申请日：2013-10-23
Applicant: INTEL CORPORATION
Inventor： Jacky Romano , Travis T. Schluessler , Guy Zadicario , Stas Gurtovoy , Liran Bachar
CPC classification number: G09G5/18 , G06F3/14 , G09G5/36 , G09G2320/103 , G09G2330/021 , G09G2340/0435 , G09G2360/16
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving image information for a current frame, determining an amount of change between the current frame and a previous based on the image information for the current frame and image information for a previous frame and determining an adjustment of a frame time based on the amount of change between the current frame and the previous frame.
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Patent Agency Ranking
公开(公告)号：US09335804B2
公开(公告)日：2016-05-10
申请号：US13783986
申请日：2013-03-04
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Ryan D. Wells , Yaakov Romano
CPC classification number: G06F1/26 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, the present invention includes a processor having a first domain with a first compute engine and a second domain with a second compute engine, where each of these domains can operate at an independent voltage and frequency. A first logic may be present to update a power bias value used to control dynamic allocation of power between the first and second domains based at least in part on a busyness of the second domain. In turn, a second logic may dynamically allocate at least a portion of a power budget for the processor between the domains based at least in part on this power bias value. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括处理器，其具有具有第一计算引擎的第一域和具有第二计算引擎的第二域，其中这些域中的每一个可以以独立的电压和频率工作。 可以存在第一逻辑来至少部分地基于第二域的繁忙来更新用于控制第一和第二域之间的功率的动态分配的功率偏置值。 反过来，第二逻辑可以至少部分地基于该功率偏差值来在区域之间动态分配处理器的功率预算的至少一部分。 描述和要求保护其他实施例。
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77.发明申请Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Power And Performance Balancing Between Multiple Processing Elements And/Or A Communication Bus 审中-公开能量效率和节能的方法，装置和系统，包括多个处理元件之间的功率和性能平衡和/或一个通信总线公开(公告)号：US20150046730A1
公开(公告)日：2015-02-12
申请号：US14526040
申请日：2014-10-28
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Russell J. Fenger
CPC classification number: G06F1/3206 , G06F1/206 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F1/329 , G06F9/50 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24
Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
Abstract translation: 这里描述了一种装置，方法和系统，用于基于测量的工作负载有效地平衡处理元件之间的性能和功率。 如果处理元件的工作负载表明它是瓶颈，则可能会增加其性能。 然而，如果包括处理元件的平台或集成电路已经在功率或热限制下运行，则性能的提高通过另一处理元件的性能的降低或上限来平衡，以保持与功率或热限制的一致性。 因此，即使在多个处理元件在功率或热限制下工作时，通过平衡功率分配来识别和缓解瓶颈。
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公开(公告)号：US12229871B2
公开(公告)日：2025-02-18
申请号：US17481656
申请日：2021-09-22
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer K P , Jonathan Kennedy , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Tomer Bar-On , Carsten Benthin , Adam T. Lake , Vasanth Ranganathan , Abhishek R. Appu
IPC: G06T15/08 , G02B27/01 , G06T15/00 , G06T15/10 , G06T15/60 , G06V20/40 , G06V40/19 , H04N13/239 , H04N13/344 , H04N23/67 , H04N25/702
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
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公开(公告)号：US20240404487A1
公开(公告)日：2024-12-05
申请号：US18736899
申请日：2024-06-07
Applicant: Intel Corporation
Inventor： Louis Feng , Altug Koker , Tomasz Janczak , Andrew T. Lauritzen , David M. Cimini , Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws , Devan Burke , Elmoustapha Ould-Ahmed-Vall , Abhishek R. Appu
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
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公开(公告)号：US20240353912A1
公开(公告)日：2024-10-24
申请号：US18657176
申请日：2024-05-07
Applicant: Intel Corporation
Inventor： Mohammed Tameem , Altug Koker , Kiran C. Veernapu , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Travis T. Schluessler , Jonathan Kennedy
IPC: G06F1/3234 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F13/16 , G06F13/40
CPC classification number: G06F1/3253 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F13/1678 , G06F13/4022
Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.
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