公开(公告)号：US20210305494A1

公开(公告)日：2021-09-30

申请号：US16828489

申请日：2020-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34

Abstract: A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.

公开(公告)号：US11081643B1

公开(公告)日：2021-08-03

申请号：US16748738

申请日：2020-01-21

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saba Zare ,  Michael Rizzolo ,  Theodorus E. Standaert ,  Daniel C. Edelstein

IPC: H01L43/12 ,  H01L27/22

Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.

公开(公告)号：US11004735B2

公开(公告)日：2021-05-11

申请号：US16131354

申请日：2018-09-14

Applicant: International Business Machines Corporation

Inventor： Cornelius B. Peethala ,  Michael Rizzolo ,  Oscar Van Der Straten ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532

Abstract: According to embodiments of the present invention, a semiconductor wafer includes a substrate and an interlayer dielectric located on the substrate. The interlayer dielectric includes an interconnect. A barrier layer is located in between the interconnect and the interlayer dielectric. A semi-liner layer is located in between the interconnect and the barrier layer. The interlayer dielectric, the interconnect, and barrier layer form a substantially planar surface opposite the substrate. The interconnect has an interconnect height from a base to the substantially planar surface and a semi-liner height of the semi-liner layer is less than the interconnect height such that liner layer does not extend to the planar surface.

公开(公告)号：US10978393B2

公开(公告)日：2021-04-13

申请号：US16131553

申请日：2018-09-14

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Takeshi Nogami ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

公开(公告)号：US10971030B2

公开(公告)日：2021-04-06

申请号：US15416046

申请日：2017-01-26

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Christopher J. Penny ,  Michael Rizzolo ,  Aldis G. Sipolins

IPC: G09B19/00 ,  G09B5/06 ,  G06F3/01 ,  G16H20/30 ,  G16H50/20 ,  G16H50/70 ,  G16H40/67

Abstract: A system and method perform remote physical training. The method includes receiving movements performed by an operator who is remotely located, and presenting the movements of the operator as movements performed by an avatar representing the operator in a virtual reality environment. The method also includes remotely monitoring the movements of the avatar, and providing real-time feedback on the movements to the operator.

公开(公告)号：US10957646B2

公开(公告)日：2021-03-23

申请号：US16782311

申请日：2020-02-05

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Cornelius Brown Peethala ,  Michael Rizzolo ,  Koichi Motoyama ,  Gen Tsutsui ,  Ruqiang Bao ,  Gangadhara Raja Muthinti ,  Lawrence A. Clevenger

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/48 ,  H01L21/768 ,  H01L21/306

Abstract: A semiconductor wafer has a top surface, a dielectric insulator, a plurality of narrow copper wires, a plurality of wide copper wires, an optical pass through layer over the top surface, and a self-aligned pattern in a photo-resist layer. The plurality of wide copper wires and the plurality of narrow copper wires are embedded in a dielectric insulator. The width of each wide copper wire is greater than the width of each narrow copper. An optical pass through layer is located over the top surface. A self-aligned pattern in a photo-resist layer, wherein photo-resist exists only in areas above the wide copper wires, is located above the optical pass through layer.

公开(公告)号：US20210035904A1

公开(公告)日：2021-02-04

申请号：US16528025

申请日：2019-07-31

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Koichi Motoyama ,  Gangadhara Raja Muthinti ,  Cornelius Brown Peethala ,  Benjamin D. Briggs ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Chamfer-less via interconnects and techniques for fabrication thereof with a protective dielectric arch are provided. In one aspect, a method of forming an interconnect includes: forming metal lines in a first dielectric; depositing an etch stop liner onto the first dielectric; depositing a second dielectric on the etch stop liner; patterning vias and a trench in the second dielectric, wherein the vias are present over at least one of the metal lines, and wherein the patterning forms patterned portions of the second dielectric/etch stop liner over at least another one of the metal lines; forming a protective dielectric arch over the at least another one of the metal lines; and filling the vias/trench with a metal(s) to form the interconnect which, due to the protective dielectric arch, is in a non-contact position with the at least another one of the metal lines. An interconnect structure is also provided.

公开(公告)号：US10833122B2

公开(公告)日：2020-11-10

申请号：US16241866

申请日：2019-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hari Prasad Amanapu ,  Raghuveer Patlolla ,  Cornelius Brown Peethala ,  Michael Rizzolo

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A substantially flat bottom electrode embedded in a dielectric for magnetoresistive random access memory (MRAM) devices includes pre-filling the contact via prior to filling the trench with tantalum nitride in a via/trench structure. The top surface of the substantially flat bottom electrode is coplanar to the top surface of the dielectric.

公开(公告)号：US10770653B1

公开(公告)日：2020-09-08

申请号：US16515461

申请日：2019-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christopher J. Penny ,  Marc A. Bergendahl ,  Michael Rizzolo ,  Christopher J. Waskiewicz

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22

Abstract: A method is presented for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region. The method includes forming protective layers in the MRAM region to preserve integrity of underlying dielectric layers, forming a bottom electrode in direct contact with the protective layers, and constructing an MRAM pillar over the bottom electrode, wherein the MRAM pillar includes a magnetic tunnel junction (MTJ) stack and a top electrode.

公开(公告)号：US10770348B2

公开(公告)日：2020-09-08

申请号：US16669708

申请日：2019-10-31

Applicant: International Business Machines Corporation

Inventor： Benjamin David Briggs ,  Lawrence A. Clevenger ,  Bartlet H. Deprospo ,  Michael Rizzolo

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  B23K26/082 ,  B23K26/00 ,  B23K26/03 ,  B23K26/70 ,  B23K26/062 ,  B23K26/352 ,  H01L23/532

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.