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    FORMATION OF AIR-GAP SPACER IN TRANSISTOR
    75.
    发明申请
    FORMATION OF AIR-GAP SPACER IN TRANSISTOR 有权
    在晶体管中形成空气隙间隙

    公开(公告)号：US20150243544A1

    公开(公告)日：2015-08-27

    申请号：US14190641

    申请日：2014-02-26

    Applicant: International Business Machines Corporation

    Inventor： Emre Alptekin ,  Viraj Sardesai ,  Cung Tran ,  Reinaldo Vega

    IPC: H01L21/768 ,  H01L21/283 ,  H01L21/28

    CPC classification number: H01L21/7682 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/78 ,  H01L2221/1063

    Abstract: Embodiments of present invention provide a method of forming air spacers in a transistor structure. The method includes forming a gate structure of a transistor on top of a semiconductor substrate; forming a first and a second disposable spacers adjacent to a first and a second sidewall of the gate structure; forming a first and a second conductive studs next to the first and the second disposable spacer; removing the first and second disposable spacers to create empty spaces between the first and second conductive studs and the gate structure; and preserving the empty spaces by forming dielectric plugs at a top of the empty spaces.

    Abstract translation: 本发明的实施例提供了一种在晶体管结构中形成空气间隔物的方法。 该方法包括在半导体衬底的顶部上形成晶体管的栅极结构; 形成邻近所述栅极结构的第一和第二侧壁的第一和第二一次性间隔件; 在第一和第二一次性间隔件旁边形成第一和第二导电柱; 去除所述第一和第二一次性间隔件以在所述第一和第二导电柱和所述栅结构之间产生空的空间; 并通过在空的空间的顶部形成电介质塞来保留空的空间。

    FinFET HAVING SUPPRESSED LEAKAGE CURRENT
    76.
    发明申请
    FinFET HAVING SUPPRESSED LEAKAGE CURRENT 有权
    具有抑制漏电流的FinFET

    公开(公告)号：US20150145064A1

    公开(公告)日：2015-05-28

    申请号：US14087655

    申请日：2013-11-22

    Applicant: International Business Machines Corporation

    Inventor： Ravikumar Ramachandran ,  Henry K. Utomo ,  Reinaldo Vega

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

    Abstract: A FinFET device which includes: a semiconductor substrate; a three dimensional fin oriented perpendicularly to the semiconductor substrate; a local trench isolation between the three dimensional fin and an adjacent three dimensional fin; a nitride layer on the local trench isolation; a gate stack wrapped around a central portion of the three dimensional fin and extending through the nitride layer; sidewall spacers adjacent to the gate stack and indirectly in contact with the nitride layer, two ends of the three dimensional fin extending from the sidewall spacers, a first end being for the source of the FET device and a second end being for a drain of the FET device; and an epitaxial layer covering each end of the three dimensional fin and being on the nitride layer. Also disclosed is a method of fabricating a FinFET device.

    Abstract translation: 一种FinFET器件，包括：半导体衬底; 垂直于半导体衬底取向的三维鳍片; 三维翅片与相邻三维翅片之间的局部沟槽隔离; 局部沟槽隔离上的氮化物层; 围绕三维翅片的中心部分并延伸穿过氮化物层的栅极堆叠; 与栅叠层相邻并间接地与氮化物层接触的侧壁间隔件，三维鳍片的两端从侧壁间隔件延伸，第一端用于FET器件的源极，第二端用于漏极 FET器件; 以及覆盖三维翅片的每一端并且在氮化物层上的外延层。 还公开了一种制造FinFET器件的方法。

    ANISOTROPIC DIELECTRIC MATERIAL GATE SPACER FOR A FIELD EFFECT TRANSISTOR
    77.
    发明申请
    ANISOTROPIC DIELECTRIC MATERIAL GATE SPACER FOR A FIELD EFFECT TRANSISTOR 有权
    用于场效应晶体管的等离子体电介质栅极间隔器

    公开(公告)号：US20150111350A1

    公开(公告)日：2015-04-23

    申请号：US14524079

    申请日：2014-10-27

    Applicant: International Business Machines Corporation

    Inventor： Emre Alptekin ,  Hari V. Mallela ,  Reinaldo Vega

    IPC: H01L21/28 ,  H01L29/66

    CPC classification number: H01L21/28008 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/772

    Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.

    Abstract translation: 可以增强栅极电极和源极和漏极区域的下部之间的电容耦合，同时抑制栅极电极和横向间隔开的元件之间的电容耦合，例如用于源极和漏极区域的接触通孔结构。 使用一次性栅极间隔物形成包括栅极和源极和漏极区的晶体管。 去除一次性栅极间隔物以形成间隔腔，其填充有各向异性介电材料以形成各向异性栅极间隔物。 各向异性介电材料与电场对准，使得各向异性介电材料的分子的纵向方向在间隔空腔内垂直对准。 各向异性栅极间隔沿垂直方向提供较高介电常数，沿水平方向提供较低介电常数。

    TAPERED INNER SPACER
    80.
    发明申请
    TAPERED INNER SPACER 有权

    公开(公告)号：US20250089329A1

    公开(公告)日：2025-03-13

    申请号：US18466215

    申请日：2023-09-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Reinaldo Vega ,  Jingyun Zhang

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A transistor includes one or more tapered inner spacers. The tapered inner spacer may include a base region that extends or protrudes beyond a plane that is coplanar with a first sidewall of the gate. The base region(s) may reduce the gate length of the gate adjacent to the base region. When two base regions are associated with the same gate, the two base regions may merge and may be between and/or isolate the gate from the underlying substrate. The tapered inner spacers may result in reduced parasitic capacitances between gate and the substrate and/or between the gate and adjacent source/drain region(s), and/or may reduce current leakage from the gate into the substrate or other underlying structure.

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