公开(公告)号：US20160163842A1

公开(公告)日：2016-06-09

申请号：US15016716

申请日：2016-02-05

Applicant: International Business Machines Corporation

Inventor： Qing Cao ,  Shu-Jen Han

IPC: H01L29/775 ,  H01L29/12 ,  H01L29/06

CPC classification number: H01L29/775 ,  H01L29/0669 ,  H01L29/125 ,  H01L51/0023 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/055 ,  H01L51/105

Abstract: A method, and the resulting structure, of making a CMOS device from carbon nanotube substrate, where a carbide contact is formed in a source drain region. The carbide is formed prior to the gate structure by reacting a glassy carbon and a metal.

Abstract translation: 一种从源极漏极区域形成碳化物接触的碳纳米管衬底制造CMOS器件的方法及其结构。 通过使玻璃碳和金属反应，在栅极结构之前形成碳化物。

公开(公告)号：US09306028B2

公开(公告)日：2016-04-05

申请号：US14661267

申请日：2015-03-18

Applicant: International Business Machines Corporation

Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/04 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

公开(公告)号：US20160093819A1

公开(公告)日：2016-03-31

申请号：US14615554

申请日：2015-02-06

Applicant: International Business Machines Corporation

Inventor： Qing Cao ,  Kangguo Cheng ,  Shu-Jen Han ,  Zhengwen Li ,  Fei Liu

IPC: H01L51/05 ,  H01L51/10 ,  H01L27/28 ,  H01L51/00

CPC classification number: H01L51/0545 ,  H01L27/283 ,  H01L51/0006 ,  H01L51/0017 ,  H01L51/0021 ,  H01L51/0048 ,  H01L51/055 ,  H01L51/0558 ,  H01L51/105

Abstract: A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device.

Abstract translation: 在半导体衬底上配置至少一个碳纳米管的方法包括在半导体器件的电介质层上沉积至少一个碳纳米管。 该方法还包括响应于向半导体器件的导电电极施加电压电位并将电位施加到半导体器件的导电半导体层，将介电层上的至少一个碳纳米管布置在电介质层上。

公开(公告)号：US20150221884A1

公开(公告)日：2015-08-06

申请号：US14169340

申请日：2014-01-31

Applicant: International Business Machines Corporation

Inventor： Shu-Jen Han ,  Wilfried E. Haensch ,  James B. Hannon

IPC: H01L51/05 ,  H01L51/00

CPC classification number: H01L51/0545 ,  B82Y10/00 ,  H01L51/0002 ,  H01L51/0048 ,  H01L51/0558

Abstract: A semiconductor device includes a substrate that extends along a first direction to define a length and second direction perpendicular to the first direction to define a height. The substrate includes a dielectric layer and at least one gate stack formed on the dielectric layer. A source contact is formed adjacent to a first side of the gate stack and a drain contact formed adjacent to an opposing second side of the gate stack. A carbon nanotube is formed on the source contact and the drain contact. A first portion of the nanotube forms a source. A second portion forms a drain. A third portion is interposed between the source and drain to define a gate channel that extends along the first direction. The source and the drain extend along the second direction and have a greater length than the gate channel.

Abstract translation: 半导体器件包括沿着第一方向延伸以限定垂直于第一方向的长度和第二方向以限定高度的衬底。 衬底包括介电层和形成在电介质层上的至少一个栅叠层。 源极触点形成为邻近栅极堆叠的第一侧，并且与栅极堆叠的相对的第二侧相邻地形成漏极接触。 在源极触点和漏极触点上形成碳纳米管。 纳米管的第一部分形成源。 第二部分形成排水管。 第三部分介于源极和漏极之间以限定沿着第一方向延伸的栅极沟道。 源极和漏极沿着第二方向延伸并且具有比栅极通道更大的长度。

公开(公告)号：US08975095B2

公开(公告)日：2015-03-10

申请号：US13904403

申请日：2013-05-29

Applicant: International Business Machines Corporation

Inventor： Shu-Jen Han ,  Ajay K. Royyuru ,  Gustavo A. Stolovitzky ,  Deqiang Wang

IPC: H01L21/66 ,  C12Q1/68 ,  G01N27/414 ,  G01N27/447

CPC classification number: C12Q1/6869 ,  G01N27/4145 ,  G01N27/4146 ,  G01N33/48721 ,  Y10S977/924 ,  C12Q2563/116 ,  C12Q2563/157 ,  C12Q2565/631

Abstract: A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current.

Abstract translation: 提供了一种用于集成设备中的基础识别的技术。 靶分子被驱动到集成器件的纳米孔中。 集成器件包括分离成左纳米线部分的纳米线和右纳米线部分，以在其间形成纳米间隙，连接到右纳米线部分的源极焊盘，连接到左纳米线部分的漏极焊盘和纳米孔。 源极焊盘，漏极焊盘，右侧的纳米线部分，左侧的纳米线部分和纳米光栅一起形成晶体管。 纳米孔是纳米孔的一部分。 测量晶体管电流，同时目标分子的单个碱基位于纳米孔的纳米隙中，单个碱基影响晶体管电流。 根据晶体管电流的变化确定单个基极的身份。

公开(公告)号：US20150060770A1

公开(公告)日：2015-03-05

申请号：US14538497

申请日：2014-11-11

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L33/00 ,  H01L33/40 ,  H01L51/00 ,  H01L33/34 ,  H01L51/52

CPC classification number: H01L33/0041 ,  H01L33/26 ,  H01L33/34 ,  H01L33/40 ,  H01L51/0048 ,  H01L51/5203 ,  H01L51/5296

Abstract: Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.

Abstract translation: 提供了碳基发光二极管（LED）及其制造技术。 一方面，提供一种LED。 LED包括基板; 衬底上的绝缘体层; 嵌入在绝缘体层中的第一底栅极和第二底栅极; 第一底栅极和第二底栅极上的栅极电介质; 在第一底栅极和第二底栅上的栅极电介质上的碳材料，其中碳材料用作LED的沟道区域; 并且金属源极和漏极接触到碳材料。

公开(公告)号：US08952431B2

公开(公告)日：2015-02-10

申请号：US13890849

申请日：2013-05-09

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/41725 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78645

Abstract: Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions.

Abstract translation: 用于形成堆叠晶体管的方法和系统。 这种方法包括在基底上形成下通道层; 在所述下通道层上形成一对垂直对准的栅极区; 在下通道材料上形成一对垂直排列的源极区域和一对垂直排列的漏极区域，每对漏极区域由绝缘体隔开; 在源极区域，漏极区域和栅极区域上形成上部沟道材料; 并提供对源极，漏极和栅极区域的电接入。

公开(公告)号：US08907381B2

公开(公告)日：2014-12-09

申请号：US14027609

申请日：2013-09-16

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Masaharu Kobayashi ,  Ko-Tao Lee ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L21/4763 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.

Abstract translation: 在一个实施例中，提供了一种形成半导体器件的方法，其可以包括在III-V半导体衬底的沟道部分上形成包括栅极结构的半导体器件。 包含III-V基底层，存在于III-V基底层上的含铝III-V半导体层的III-V半导体衬底和III-V沟道层。 在栅极结构的相对侧上氧化含铝III-V族半导体层的一部分。 在被氧化的含铝III-V族半导体层的部分上形成凸起的源区和升高的漏极区。 与升高的源极区域和升高的漏极区域形成互连。

公开(公告)号：US20140332855A1

公开(公告)日：2014-11-13

申请号：US13888657

申请日：2013-05-07

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Masaharu Kobayashi ,  Ko-Tao Lee ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L29/20

CPC classification number: H01L29/78 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.

Abstract translation: 在一个实施例中，提供了一种形成半导体器件的方法，其可以包括在III-V半导体衬底的沟道部分上形成包括栅极结构的半导体器件。 包含III-V基底层，存在于III-V基底层上的含铝III-V半导体层的III-V半导体衬底和III-V沟道层。 在栅极结构的相对侧上氧化含铝III-V族半导体层的一部分。 在被氧化的含铝III-V族半导体层的部分上形成凸起的源区和升高的漏极区。 与升高的源极区域和升高的漏极区域形成互连。

公开(公告)号：US20140326604A1

公开(公告)日：2014-11-06

申请号：US13904403

申请日：2013-05-29

Applicant: International Business Machines Corporation

Inventor： Shu-Jen Han ,  Ajay K. Royyuru ,  Gustavo A. Stolovitzky ,  Deqiang Wang

IPC: C12Q1/68 ,  G01N27/447

CPC classification number: C12Q1/6869 ,  G01N27/4145 ,  G01N27/4146 ,  G01N33/48721 ,  Y10S977/924 ,  C12Q2563/116 ,  C12Q2563/157 ,  C12Q2565/631

Abstract: A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current.

Abstract translation: 提供了一种用于集成设备中的基础识别的技术。 靶分子被驱动到集成器件的纳米孔中。 集成器件包括分离成左纳米线部分的纳米线和右纳米线部分，以在其间形成纳米间隙，连接到右纳米线部分的源极焊盘，连接到左纳米线部分的漏极焊盘和纳米孔。 源极焊盘，漏极焊盘，右侧的纳米线部分，左侧的纳米线部分和纳米光栅一起形成晶体管。 纳米孔是纳米孔的一部分。 测量晶体管电流，同时目标分子的单个碱基位于纳米孔的纳米隙中，单个碱基影响晶体管电流。 根据晶体管电流的变化确定单个基极的身份。