公开(公告)号：US20220399278A1

公开(公告)日：2022-12-15

申请号：US17345925

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Brandon C. Marin

IPC: H01L23/538

Abstract: An electronic substrate may be fabricated having a primary interposer comprising a laminate with a metal via through the laminate, two or more secondary interposers attached to a first side of the primary interposer, where respective sidewalls of the two or more secondary interposers define one or more recesses over the primary interposer, and an embedded component within a recess of the one or more recesses defined by the respective sidewalls of the two or more secondary interposers. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

公开(公告)号：US20220093520A1

公开(公告)日：2022-03-24

申请号：US17026703

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC: H01L23/538 ,  H05K1/11 ,  H01L21/768

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US11158444B2

公开(公告)日：2021-10-26

申请号：US15894418

申请日：2018-02-12

Applicant: INTEL CORPORATION

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498 ,  H01F17/00

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.

公开(公告)号：US20210091030A1

公开(公告)日：2021-03-25

申请号：US16582865

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Gang Duan ,  Sameer Paital

IPC: H01L23/00

Abstract: Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system.

公开(公告)号：US20190252102A1

公开(公告)日：2019-08-15

申请号：US15894418

申请日：2018-02-12

Applicant: INTEL CORPORATION

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01F1/20 ,  H01F27/2804 ,  H01F2027/2809 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.

公开(公告)号：US10290557B2

公开(公告)日：2019-05-14

申请号：US15549970

申请日：2015-03-09

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Trina Ghosh Dastidar ,  Dilan Seneviratne ,  Yonggang Li ,  Sirisha Chava

IPC: H05K3/10 ,  H01L23/14 ,  H05K3/06 ,  H05K3/18 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20250105209A1

公开(公告)日：2025-03-27

申请号：US18475373

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Gang Duan ,  Yosuke Kanaoka ,  Minglu Liu ,  Srinivas V. Pietambaram ,  Brandon C. Marin ,  Bohan Shan ,  Haobo Chen ,  Jeremy Ecton ,  Benjamin T. Duong ,  Suddhasattwa Nad

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/42 ,  H01L23/538 ,  H10B80/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.

公开(公告)号：US20250096143A1

公开(公告)日：2025-03-20

申请号：US18470668

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Tarek A. Ibrahim ,  Srinivas V. Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48

Abstract: A microelectronic assembly includes a bridge die embedded in a substrate. The substrate includes a doped dielectric material in a layer or region directly below the bridge die, and in a layer near an upper face of the bridge die. A cavity is formed in the upper layer of the doped dielectric material for embedding the bridge die, exposing the lower layer of the doped dielectric material. After cavity formation, a selective metallization of the lower and upper layers of the doped dielectric material is performed, providing well-aligned metal layers in the region of the bridge die and the region around the bridge die.

公开(公告)号：US20240363995A1

公开(公告)日：2024-10-31

申请号：US18306399

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Bai Nie ,  Jeremy Ecton ,  Brandon C. Marin ,  Mohammad Mamunur Rahman

IPC: H01Q1/22 ,  G06F1/16

CPC classification number: H01Q1/2283 ,  G06F1/1698

Abstract: Disclosed herein are antenna units, microelectronic assemblies, and communication devices that may enable RF chip-to-chip communications in a compact form factor. An example microelectronic assembly may include a microelectronic component (e.g., a package substrate, a circuit board, and interposer, or a die) and an antenna unit that may be separately fabricated and integrated in a recess in the microelectronic component, enabling increased degrees of design freedom and improved yield. An example antenna unit may include a glass core having a first face and an opposing second face, a tapered opening extending between the first face and the second face of the glass core, and a layer of an electrically conductive material on sidewalls of the opening, where the opening in the glass core lined with the layer of the electrically conductive material forms a horn antenna integrated in the glass core.

公开(公告)号：US12057252B2

公开(公告)日：2024-08-06

申请号：US17029870

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC: H05K1/02 ,  H01F1/37 ,  H01F17/04 ,  H01F17/06 ,  H01F27/24 ,  H01F27/245 ,  H01F27/28 ,  H01F27/29 ,  H01F41/24 ,  H01F41/32 ,  H01L23/15 ,  H01L23/498 ,  H01L23/64 ,  H05K1/09 ,  H05K3/02 ,  H05K3/42

CPC classification number: H01F27/2804 ,  H01F41/32 ,  H01L23/49827 ,  H01L23/645 ,  H01F2027/2809 ,  H01L23/49816

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.