公开(公告)号：US08841723B2

公开(公告)日：2014-09-23

申请号：US12720834

申请日：2010-03-10

申请人： Tsung-Yi Huang ,  Huan-Ping Chu ,  Ching-Yao Yang ,  Hung-Der Su

发明人： Tsung-Yi Huang ,  Huan-Ping Chu ,  Ching-Yao Yang ,  Hung-Der Su

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0878 ,  H01L29/66681

摘要： The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage.

摘要翻译： 本发明公开了一种具有增加的穿通电压的LDMOS器件及其制造方法。 LDMOS器件包括：衬底; 在基板中形成的第一导电类型的阱; 形成在衬底中的隔离区; 井中的第二导电类型的体区; 身体的一个来源; 井中排水 基板上的栅极结构; 以及在身体区域下面的第一导电型掺杂区域，用于增加穿通电压。

公开(公告)号：US20140175545A1

公开(公告)日：2014-06-26

申请号：US13726579

申请日：2012-12-25

申请人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

摘要翻译： 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和 第一导电型浮动区域。 浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

公开(公告)号：US20140159048A1

公开(公告)日：2014-06-12

申请号：US13898374

申请日：2013-05-20

申请人： Chih-Fang Huang ,  Po-Chin Peng ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  K.C. Chang ,  Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang ,  Tsung-Yu Yang ,  Ting-Fu Chang

发明人： Chih-Fang Huang ,  Po-Chin Peng ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  K.C. Chang ,  Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang ,  Tsung-Yu Yang ,  Ting-Fu Chang

IPC分类号： H01L29/778

CPC分类号： H01L29/66462 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/7789

摘要： The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.

摘要翻译： 本发明公开了一种高电子迁移率晶体管（HEMT）及其制造方法。 HEMT器件包括：衬底，第一氮化镓（GaN）层; P型GaN层，第二GaN层，势垒层，栅极，源极和漏极。 第一GaN层形成在基板上，并且具有从横截面视图的阶梯状轮廓。 P型GaN层形成在阶梯状轮廓的上台阶面上，具有垂直侧壁。 第二GaN层形成在P型GaN层上。 阻挡层形成在第二GaN层上。 在阻挡层与第一和第二GaN层之间的接合处形成二维电子气体区域。 门形成在垂直侧壁的外侧。

公开(公告)号：US20140117443A1

公开(公告)日：2014-05-01

申请号：US14146512

申请日：2014-01-02

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

公开(公告)号：US06828198B2

公开(公告)日：2004-12-07

申请号：US10392120

申请日：2003-03-19

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/28123 ,  H01L21/32139

摘要： A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

公开(公告)号：US06582995B2

公开(公告)日：2003-06-24

申请号：US09903125

申请日：2001-07-11

申请人： Ting-Hua Hsieh ,  Hung-Der Su ,  Carlos H. Diaz

发明人： Ting-Hua Hsieh ,  Hung-Der Su ,  Carlos H. Diaz

IPC分类号： H01L21335

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

摘要： Within a method for fabricating a microelectronic fabrication comprising a topographic microelectronic structure formed over a substrate, there is implanted, while employing a first ion implant method and while masking a portion of the substrate adjacent the topographic microelectronic structure but not masking the topographic microelectronic structure, the topographic microelectronic structure to form an ion implanted topographic microelectronic structure without implanting the substrate. There is also implanted, while employing a second ion implant method, the portion of the substrate adjacent the topographic microelectronic substrate to form therein an ion implant structure. The method is particularly useful for fabricating source/drain regions with shallow junctions within field effect transistor (FET) devices.

摘要翻译： 在制造包括形成在衬底上的形貌微电子结构的微电子制造的方法中，注入植入，同时采用第一离子注入方法，同时掩盖与形貌微电子结构相邻但不掩盖地形微电子结构的衬底的一部分， 地形微电子结构，以形成离子注入的地形微电子结构，而不会植入衬底。 在采用第二离子注入方法的同时，植入衬底的部分与形貌微电子衬底相邻以在其中形成离子注入结构。 该方法对于在场效应晶体管（FET）器件中制造具有浅结的源极/漏极区域特别有用。

公开(公告)号：US06251744B1

公开(公告)日：2001-06-26

申请号：US09356870

申请日：1999-07-19

申请人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L2176

CPC分类号： H01L21/76213

摘要： A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

摘要翻译： 在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。 在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。 去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。 牺牲氧化物层沉积在半导体衬底的表面上。 在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。

公开(公告)号：US06190969B1

公开(公告)日：2001-02-20

申请号：US09257722

申请日：1999-02-25

申请人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L29/66825

摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.

公开(公告)号：US06130168A

公开(公告)日：2000-10-10

申请号：US349844

申请日：1999-07-08

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC分类号： H01L21/32 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/302

CPC分类号： H01L27/11526 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/954

摘要： A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer. A second polysilicon layer is deposited over the ONO layer in the memory area, over the thin gate oxide layer in the low voltage area, and over the thick gate oxide layer in the high voltage area. The second polysilicon layer, ONO layer and first polysilicon layer in the memory cell area are patterned to form a control gate overlying a floating gate separated by the ONO layer. The second polysilicon layer is patterned to form a low voltage transistor in the low voltage area and a high voltage transistor in the high voltage area.

摘要翻译： 描述了为高压和低压晶体管形成差分栅极氧化物厚度的新方法。 提供半导体衬底，其中衬底的有源区域通过浅沟槽隔离区域与其它有源区域隔离。 沉积在衬底表面上的隧道氧化物层上的多晶硅层。 去除多晶硅和隧道氧化物层，除了在存储单元区域中。 沉积在存储单元区域中的多晶硅层和低电压和高电压区域的衬底表面上的ONO层。 在高电压区域中去除ONO层。 衬底在高压区域被氧化以形成厚的栅极氧化物层。 此后，在低电压区域中去除ONO层，并且衬底被氧化以形成薄的栅极氧化物层。 第二多晶硅层沉积在存储区域中的ONO层上，在低电压区域的薄栅极氧化物层上方，以及高电压区域中的厚栅极氧化物层上方。 将存储单元区域中的第二多晶硅层，ONO层和第一多晶硅层图案化以形成覆盖由ONO层分离的浮动栅极的控制栅极。 将第二多晶硅层图案化以在低电压区域中形成低压晶体管，并在高电压区域形成高压晶体管。

公开(公告)号：US09627524B2

公开(公告)日：2017-04-18

申请号：US12715501

申请日：2010-03-02

申请人： Tsung-Yi Huang ,  Huan-Ping Chu ,  Ching-Yao Yang ,  Hung-Der Su

发明人： Tsung-Yi Huang ,  Huan-Ping Chu ,  Ching-Yao Yang ,  Hung-Der Su

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/7833 ,  H01L29/7835

摘要： The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device).