公开(公告)号：US06292116B1

公开(公告)日：2001-09-18

申请号：US09571766

申请日：2000-05-16

申请人： Bonnie I. Wang ,  Chiakang Sung ,  In Whan Kim ,  Wayne Yeung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

发明人： Bonnie I. Wang ,  Chiakang Sung ,  In Whan Kim ,  Wayne Yeung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

IPC分类号： H03M900

CPC分类号： H03K19/1774 ,  H03K19/17744 ,  H03M9/00

摘要： Techniques and circuitry are provided to handle high frequency input data. The techniques and circuitry take a high-frequency serial input data stream and covert it into parallel form for handling within the integrated circuit. The circuitry ensures the high frequency data is strobed properly by accounting for skew between the high frequency data input and clock input. In an implementation, multiple clock strobes are generated having the same frequency but different phase. A predetermined series of bits is input to the high frequency input into the circuitry for training. One of the multiple clock strobes is selected based on which one correctly determines the bits in the predetermined input data stream. This clock strobe is selected to strobe the high frequency data input for the integrated circuit. In an embodiment, the high frequency data input is an LVDS input of a programmable logic integrated circuit.

摘要翻译： 提供技术和电路来处理高频输入数据。 技术和电路采用高频串行输入数据流，并将其隐藏为并行形式，用于集成电路内的处理。 该电路通过考虑高频数据输入和时钟输入之间的偏斜，确保高频数据正确选通。 在一个实现中，产生具有相同频率但相位相差的多个时钟选通。 将预定的一系列比特输入到用于训练的电路中的高频输入。 基于哪个正确地确定预定输入数据流中的比特来选择多个时钟选通中的一个。 选择该时钟选通脉冲以选通集成电路的高频数据输入。 在一个实施例中，高频数据输入是可编程逻辑集成电路的LVDS输入。

公开(公告)号：US6114915A

公开(公告)日：2000-09-05

申请号：US285180

申请日：1999-03-23

申请人： Joseph Huang ,  Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Wayne Yeung ,  In Whan Kim

发明人： Joseph Huang ,  Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Wayne Yeung ,  In Whan Kim

IPC分类号： H03K5/00 ,  H03K23/66 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/183 ,  H03K21/38

CPC分类号： H03K23/665 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/0997 ,  H03L7/183 ,  H03K2005/00045

摘要： Method and circuitry for a frequency synthesizer having wide operating frequency range. The frequency synthesizer uses multiple programmable loadable counters in a phase-locked loop arrangement to generate any combination of clock frequencies based on user programmed values. In a specific embodiment of the invention, the phase-locked loop includes a voltage-controlled oscillator with a built-in programmable phase shift. The present invention further provides a preferred embodiment for a high speed loadable down counter for use in the frequency synthesizer.

摘要翻译： 具有宽工作频率范围的频率合成器的方法和电路。 频率合成器使用多个可编程可加载计数器进行锁相环布置，以根据用户编程的值生成时钟频率的任意组合。 在本发明的具体实施例中，锁相环包括具有内置可编程相移的压控振荡器。 本发明还提供了一种用于频率合成器中的高速可加载递减计数器的优选实施例。

公开(公告)号：US09711189B1

公开(公告)日：2017-07-18

申请号：US13209307

申请日：2011-08-12

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Yan Chong ,  Joseph Huang ,  Khai Nguyen ,  Pradeep Nagarajan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Yan Chong ,  Joseph Huang ,  Khai Nguyen ,  Pradeep Nagarajan

IPC分类号： G11C5/14 ,  G11C11/4074

CPC分类号： G11C5/147 ,  G11C11/4074 ,  G11C19/00 ,  G11C29/021 ,  G11C29/028

摘要： A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.

公开(公告)号：US08487665B2

公开(公告)日：2013-07-16

申请号：US13149168

申请日：2011-05-31

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03B1/00

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

公开(公告)号：US07315188B2

公开(公告)日：2008-01-01

申请号：US11446483

申请日：2006-06-02

申请人： Bonnie L. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie L. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03B1/00

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US07205802B1

公开(公告)日：2007-04-17

申请号：US11349516

申请日：2006-02-03

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

IPC分类号： H03L7/06

CPC分类号： H03K5/135 ,  H03K5/1252 ,  H03L7/0805 ,  H03L7/0814

摘要： A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

摘要翻译： 一种用于在DDR应用中更新由延迟链接收的控制信号的方法和装置。 寄存器用于调节到延迟链的控制信号。 当信号没有通过延迟链时，寄存器仅更新延迟链上的信号。 此外，本发明涉及一种延迟电路，其使用彼此并联连接的多个PMOS和NMOS晶体管以及提供所需延迟的反相器。 提供的延迟是通过顺序关闭/接通一系列NMOS / PMOS晶体管对来实现的。

公开(公告)号：US07116135B2

公开(公告)日：2006-10-03

申请号：US10886015

申请日：2004-07-06

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03B1/00

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

公开(公告)号：US07109765B1

公开(公告)日：2006-09-19

申请号：US10996186

申请日：2004-11-22

申请人： Bonnie I Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

发明人： Bonnie I Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

IPC分类号： H03L7/06

CPC分类号： H03L7/0891 ,  H03K19/1774 ,  H03L7/0812 ,  H03L7/0996

摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

公开(公告)号：US07098690B2

公开(公告)日：2006-08-29

申请号：US11025774

申请日：2004-12-29

申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速I / O模式（如双数据速率和零总线周转）进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

公开(公告)号：US07088140B1

公开(公告)日：2006-08-08

申请号：US10794987

申请日：2004-03-04

申请人： Khai Nguyen ,  Chiakang Sung ,  Gopi Rangan ,  Tzung-Chin Chang

发明人： Khai Nguyen ,  Chiakang Sung ,  Gopi Rangan ,  Tzung-Chin Chang

IPC分类号： H03K19/0175

CPC分类号： H03K19/17744 ,  H03K19/00315 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

摘要： Circuits, methods, and apparatus that provide output drivers that consume relatively little integrated circuit area and provide fast output switching. An exemplary embodiment provides an output driver including pull-up and pull-down devices, each device driven by a pre-driver stage. The pre-driver for the pull-down device is supplied from an auxiliary power supply, which has a higher voltage than the supply seen by the pull-up device. The pre-driver for the pull-down is biased by a voltage that tracks the higher of the auxiliary and output supplies. In some embodiments, the output driver may be part of an input/output cell. In that case, the well for the pull-up device is biased by a voltage that tracks the highest of the output supply and input received voltage, while the pull-up predriver circuit bias is the higher between the auxiliary and output supplies and the input received voltage.

摘要翻译： 提供输出驱动器的电路，方法和装置，其消耗相对较小的集成电路面积并提供快速输出切换。 示例性实施例提供了包括上拉和下拉装置的输出驱动器，每个装置由预驱动器级驱动。 用于下拉装置的预驱动器由辅助电源供电，辅助电源的电压高于上拉装置所看到的电源电压。 用于下拉的预驱动器被跟踪较高的辅助和输出电源的电压偏置。 在一些实施例中，输出驱动器可以是输入/输出单元的一部分。 在这种情况下，上拉器件的阱被跟踪输出电源的最高电压和输入接收电压的电压偏置，而上拉预驱动电路偏置在辅助和输出电源和输入之间较高 接收电压。