公开(公告)号：US08133772B2

公开(公告)日：2012-03-13

申请号：US13075271

申请日：2011-03-30

申请人： John E. Barth, Jr. ,  Kerry Bernstein ,  Ethan H. Cannon ,  Francis R. White

发明人： John E. Barth, Jr. ,  Kerry Bernstein ,  Ethan H. Cannon ,  Francis R. White

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

公开(公告)号：US08106505B2

公开(公告)日：2012-01-31

申请号：US11933107

申请日：2007-10-31

申请人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

发明人： Kerry Bernstein ,  Thomas Brunschwiler ,  Bruno Michel

IPC分类号： H01L23/34

CPC分类号： H01L23/49827 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15159 ,  H01L2924/3011

摘要： An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

摘要翻译： 一种组件，包括集成电路的芯片，包括集成电路的壳体，并且具有形成在芯片的一侧的上部和形成在芯片的另一侧的下部，用于电连接的多个贯通晶片通孔（TWV） 芯片的集成电路和壳体的集成电路，以及连接到壳体的卡，用于将壳体电连接到系统板。

公开(公告)号：US08053819B2

公开(公告)日：2011-11-08

申请号：US12120899

申请日：2008-05-15

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

摘要翻译： 具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

公开(公告)号：US07989865B2

公开(公告)日：2011-08-02

申请号：US12200538

申请日：2008-08-28

申请人： John Edward Barth, Jr. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

发明人： John Edward Barth, Jr. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

公开(公告)号：US07989312B2

公开(公告)日：2011-08-02

申请号：US12612957

申请日：2009-11-05

申请人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

摘要翻译： 一种半导体结构及其制造方法。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US07964466B2

公开(公告)日：2011-06-21

申请号：US12762427

申请日：2010-04-19

申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。

公开(公告)号：US20110026806A1

公开(公告)日：2011-02-03

申请号：US12512168

申请日：2009-07-30

申请人： Kerry Bernstein ,  James Culp ,  David F. Heidel ,  Dirk Pfeiffer ,  Anthony D. Polson ,  Peilin Song ,  Franco Stellari ,  Robert L. Wisnieff

发明人： Kerry Bernstein ,  James Culp ,  David F. Heidel ,  Dirk Pfeiffer ,  Anthony D. Polson ,  Peilin Song ,  Franco Stellari ,  Robert L. Wisnieff

IPC分类号： G03F9/00 ,  G06F19/00

CPC分类号： G01R31/311

摘要： An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.

摘要翻译： 通过测量要测试的物理电路来获得待测试电路的发射图。 通过测量物理参考电路或通过模拟从参考电路预期的发射来获得参考电路的发射图。 与参考电路相比，要测试的电路的发射图与参考电路的发射图进行比较，以确定待测电路中的变化的存在。

公开(公告)号：US07865694B2

公开(公告)日：2011-01-04

申请号：US11382967

申请日：2006-05-12

申请人： Kerry Bernstein ,  Timothy J. Dalton ,  Marc R. Faucher ,  Peter A. Sandon

发明人： Kerry Bernstein ,  Timothy J. Dalton ,  Marc R. Faucher ,  Peter A. Sandon

IPC分类号： G06F15/76

CPC分类号： H01L25/0652 ,  H01L25/18 ,  H01L2225/06562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-layer silicon stack architecture includes one or more processing layers including one or more computing elements; one or more networking layers disposed between the processing layers, the network layer includes one or more networking elements, wherein each computing element includes a plurality of network connections to adjacently disposed networking elements.

摘要翻译： 多层硅堆栈架构包括一个或多个包括一个或多个计算元件的处理层; 布置在处理层之间的一个或多个网络层，网络层包括一个或多个网络元件，其中每个计算元件包括到相邻布置的网络元件的多个网络连接。

公开(公告)号：US20100011278A1

公开(公告)日：2010-01-14

申请号：US12170462

申请日：2008-07-10

申请人： Kerry Bernstein ,  Norman J. Rohrer

发明人： Kerry Bernstein ,  Norman J. Rohrer

IPC分类号： H03M13/15 ,  G06F11/07

CPC分类号： H03M13/15 ,  G06F11/1008 ,  H03M13/098 ,  H03M13/13 ,  H03M13/1505 ,  H03M13/19

摘要： An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.

摘要翻译： 在处理器进入睡眠模式之前，将物理逻辑寄存器和锁存内容逐行生成在处理器内的处理器内，生成错误校正码，并检查后来生成的校验码位 处理器唤醒时出现软错误，例如作为上电顺序的一部分。

公开(公告)号：US20090305462A1

公开(公告)日：2009-12-10

申请号：US12542235

申请日：2009-08-17

申请人： Robert J. Bucki ,  Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Eric Robinson

发明人： Robert J. Bucki ,  Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Eric Robinson

IPC分类号： H01L21/00 ,  H01L21/46

CPC分类号： H01L25/0657 ,  G11C15/00 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68368 ,  H01L2224/24226 ,  H01L2224/80896 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.

摘要翻译： 提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。 多端口CAM单元在本发明中是通过利用三维积分来实现的，其中多个有源电路层是垂直堆叠的，并且使用垂直排列的互连将器件从堆叠层之一连接到另一层叠层中的另一个器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。 这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。 每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。