公开(公告)号：US20240420790A1

公开(公告)日：2024-12-19

申请号：US18635869

申请日：2024-04-15

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Eric J. Stave ,  Timothy M. Hollis ,  Chulkyu Lee ,  Chris Gregory Holub

IPC: G11C29/42 ,  G11C29/12

Abstract: Systems and methods include receiving data bits at an input pin of a semiconductor device from a host device. The received data is latched in latch circuitries of the semiconductor device that at least partially implements an equalizer to aid in interpreting the received data bits. A first latched bit latched from the first received bit of the received bits is transmitted from the latch circuitries to self-calibration circuitry. The first received bit is also latched in error evaluation circuitry as a second latched bit. The second latched bit is transmitted from the error evaluation circuitry to the self-calibration circuitry. The self-calibration circuitry determines settings for the equalizer without involving the host device in determining the settings after the host device sends the data bits.

公开(公告)号：US20240290752A1

公开(公告)日：2024-08-29

申请号：US18658874

申请日：2024-05-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.

公开(公告)号：US20240249758A1

公开(公告)日：2024-07-25

申请号：US18623355

申请日：2024-04-01

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US12021668B2

公开(公告)日：2024-06-25

申请号：US17562588

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/03057 ,  H04L25/4917

Abstract: Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit can be coupled between an output and an input of a middle slicer. In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye of the PAM4 signal. The other two eyes thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.

公开(公告)号：US11984428B2

公开(公告)日：2024-05-14

申请号：US18063505

申请日：2022-12-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.

公开(公告)号：US11979979B2

公开(公告)日：2024-05-07

申请号：US17238797

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： M. Ataul Karim ,  David K. Ovard ,  Aparna U. Limaye ,  Timothy M. Hollis

IPC: H05K1/02 ,  H04B3/32 ,  H04B3/487

CPC classification number: H05K1/0233 ,  H04B3/32 ,  H04B3/487 ,  H05K1/0228

Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.

公开(公告)号：US20240045620A1

公开(公告)日：2024-02-08

申请号：US18490589

申请日：2023-10-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F1/04 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F1/04 ,  G06F13/1689 ,  G06F2213/16

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

公开(公告)号：US11837580B2

公开(公告)日：2023-12-05

申请号：US17349657

申请日：2021-06-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.

公开(公告)号：US11675728B2

公开(公告)日：2023-06-13

申请号：US17360994

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F13/42 ,  G06F13/16 ,  G11C8/06 ,  G06F1/08 ,  G11C8/18

CPC classification number: G06F13/4234 ,  G06F1/08 ,  G06F13/1689 ,  G06F13/4282 ,  G11C8/06 ,  G11C8/18

Abstract: Methods, systems, and apparatuses related to configured dual register clock driver (RCD) devices on a single memory subsystem using different configuration information are described. In some examples, configuration of the two RCD devices with different configuration information may include use of a serial data bus to receive and store first RCD configuration data, which is provided to both of the RCD devices to configure one or more parameters of each respective RCD device. One of the RCD devices may receive second configuration data via a command and address bus to independently update the one or more configuration parameters of one of the two RCD devices.

公开(公告)号：US20230014013A1

公开(公告)日：2023-01-19

申请号：US17936048

申请日：2022-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C8/06

Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.