公开(公告)号：US5831306A

公开(公告)日：1998-11-03

申请号：US823946

申请日：1997-03-25

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L29/7835

摘要： An asymmetrical IGFET including a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.

摘要翻译： 公开了一种包括轻掺杂漏极区域，重掺杂源极和漏极区域以及超重掺杂源极区域的非对称IGFET。 优选地，轻掺杂漏极区域和重掺杂源极区域提供通道结。 制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以将 轻掺杂源区域分成重掺杂源区，而不掺杂轻掺杂漏极区，分别与第一和第二侧壁相邻形成第一和第二间隔，并施加第三离子注入以将重掺杂源区的一部分转换到外部 所述第一间隔物进入超重掺杂源区，而不掺杂所述第一间隔物下方的重掺杂源区的一部分，以及将所述第二间隔区外部的所述轻掺杂漏极区的一部分转换为重掺杂漏极区，而不掺杂 第二间隔物下方的轻掺杂漏极区的部分。 有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

公开(公告)号：US5445975A

公开(公告)日：1995-08-29

申请号：US206977

申请日：1994-03-07

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Derick J. Wristers

IPC分类号： H01L21/322 ,  H01L21/324

CPC分类号： H01L21/3225 ,  Y10S148/06

摘要： A method is provided for pre-process denudation and process-induced gettering of a CZ silicon wafer having one or more monolithic devices embodied therein. Pre-process denudation is performed in a hydrogen ambient to out-diffuse oxygen as well as to maintain interstitial silicon flux away from the substrate surface. Process-induced gettering is performed at a low temperature to ensure stacking faults and surface irregularities do not arise from interstitial silicon bonding at the surface prior to gate oxidation. The third step of the denudation/gettering cycle involving precipitate growth is thereby delayed or forestalled until the field oxide is grown. Any changes or movement in oxygen and/or interstitial silicon within or near the substrate surface occurring after polysilicon deposition will have minimal effect upon the established gate oxide. Accordingly, gate oxide integrity (e.g., breakdown voltage and uniformity) are enhanced by the present process.

摘要翻译： 提供了一种用于预处理剥蚀和具有其中实施的具有一个或多个单片器件的CZ硅晶片的工艺诱导吸除的方法。 在氢环境中进行预处理剥蚀以使氧扩散以及保持间隙硅熔剂远离衬底表面。 在低温下进行过程诱导的吸气以确保堆垛层错，并且在栅极氧化之前的表面处的间隙硅键不会产生表面不规则性。 涉及沉淀生长的剥蚀/吸除循环的第三步骤因此被延迟或预防，直到场氧化物生长。 在多晶硅沉积之后发生的衬底表面内或附近的氧和/或间隙硅中的任何变化或移动对所建立的栅极氧化物的影响最小。 因此，通过本方法增强栅极氧化物完整性（例如，击穿电压和均匀性）。

公开(公告)号：US06323519B1

公开(公告)日：2001-11-27

申请号：US09177871

申请日：1998-10-23

申请人： Mark I. Gardner ,  Derick J. Wristers ,  Charles E. May

发明人： Mark I. Gardner ,  Derick J. Wristers ,  Charles E. May

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/3144 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656

摘要： A transistor and a method for making a transistor are described. A gate conductor is patterned over a gate dielectric upon a semiconductor substrate. Dopant impurity distributions self-aligned to the gate conductor may be introduced. A conformal oxide having thickness between about 100 angstroms and 500 angstroms is deposited over the gate conductor and substrate. The oxide is exposed to a nitrogen-bearing plasma for conversion to nitrided oxide. Anisotropic etching may then be used to form ultrathin, nitrided oxide spacers. Introduction of a second dopant impurity distribution may be performed to create source-drain regions having narrow LDD regions, and resulting decreased series resistance and increased saturated drain current. Thicker spacers or spacers combining oxide and nitrided oxide portions may firther be formed by repeated deposition of thin conformal oxides. The presence of nitrogen in nitrided oxide portions of the spacers is believed to help prevent dopant outdiffusion from adjacent silicon, prevent silicide bridging across spacers, and increase resistance of the spacers to oxide etchants.

摘要翻译： 描述晶体管和制造晶体管的方法。 在半导体衬底上的栅极电介质上形成栅极导体。 可以引入与栅极导体自对准的掺杂杂质分布。 在栅极导体和衬底上沉积厚度在约100埃和500埃之间的共形氧化物。 将氧化物暴露于含氮等离子体以转化为氮化氧化物。 然后可以使用各向异性蚀刻来形成超薄，氮化的氧化物间隔物。 可以引入第二掺杂剂杂质分布以产生具有窄LDD区域的源极 - 漏极区域，并且导致降低的串联电阻和增加的饱和漏极电流。 结合氧化物和氮化氧化物部分的较厚的间隔物或间隔物可以通过重复沉积薄的共形氧化物而形成。 认为间隔物的氮化氧化物部分中存在氮气有助于防止掺杂剂从相邻硅中扩散，从而防止跨越间隔物的硅化物桥接，并增加间隔物对氧化物蚀刻剂的电阻。

公开(公告)号：US06225188B1

公开(公告)日：2001-05-01

申请号：US09524447

申请日：2000-03-14

申请人： Derick J. Wristers ,  H. Jim Fulford ,  Mark I. Gardner

发明人： Derick J. Wristers ,  H. Jim Fulford ,  Mark I. Gardner

IPC分类号： H01L21265

CPC分类号： H01L21/76237

摘要： A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative proximal to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.

摘要翻译： 提供其中在半导体衬底中形成至少一个隔离结构的半导体工艺。 氧离子种类被引入半导体衬底的靠近隔离结构的部分，优选通过使用离子注入到倾斜或倾斜的衬底中。 然后在半导体衬底的上表面上形成栅介质层。 在半导体衬底的近端部分存在含氧物质增加了部分相对于离开隔离结构远端的部分氧化速率的氧化速率。 以这种方式，在半导体衬底的近端部分上的栅极电介质的第一厚度大于半导体衬底的剩余部分上的栅极氧化物层的第二厚度。 与隔离沟槽的不连续性相邻的增加的氧化物厚度减小了跨过氧化物的电场。

公开(公告)号：US6160300A

公开(公告)日：2000-12-12

申请号：US238081

申请日：1999-01-26

申请人： Mark I. Gardner ,  Derick J. Wristers ,  Charles E. May

发明人： Mark I. Gardner ,  Derick J. Wristers ,  Charles E. May

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L29/49 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28035 ,  H01L21/321 ,  H01L29/4925 ,  H01L29/6659

摘要： A fabrication process and transistor are described in which a transistor having a diffusion barrier located in the bottom layer of a stacked (i.e., multi-layer) gate conductor is formed, thereby reducing the diffusion of dopants from the gate conductor to the underlying channel region. In a general embodiment, multiple gate conductor layers are formed and arranged in a vertical stack, and a diffusion barrier is introduced into one or more layers of the stack. In a preferred dual-layer embodiment, a first gate conductor layer (i.e., the bottom layer) having a first thickness is deposited upon a gate dielectric layer. An argon distribution is then introduced into the first gate conductor layer to form an argon diffusion barrier in the first gate conductor layer. A second gate conductor layer having a second thickness is then deposited upon the first gate conductor layer. The second thickness is preferably greater than the first thickness, which in turn is greater than the thickness of the argon diffusion barrier residing within the first gate conductors layer. The thickness of the first gate conductor layer is controlled to facilitate location of the diffusion barrier, thereby presenting numerous advantages over conventional barrier formation techniques.

摘要翻译： 描述了一种制造工艺和晶体管，其中形成具有位于层叠（即，多层）栅极导体的底层中的扩散阻挡层的晶体管，从而减少掺杂剂从栅极导体到底层沟道区域的扩散 。 在一般实施例中，多个栅极导体层形成并布置成垂直堆叠，并且扩散阻挡层被引入堆叠的一个或多个层中。 在优选的双层实施例中，具有第一厚度的第一栅极导体层（即，底层）沉积在栅极介电层上。 然后将氩分布引入到第一栅极导体层中，以在第一栅极导体层中形成氩扩散阻挡层。 然后将具有第二厚度的第二栅极导体层沉积在第一栅极导体层上。 第二厚度优选地大于第一厚度，其又大于驻留在第一栅极导体层内的氩扩散阻挡层的厚度。 控制第一栅极导体层的厚度以便于扩散阻挡层的定位，从而与常规屏障形成技术相比具有许多优点。

公开(公告)号：US6107130A

公开(公告)日：2000-08-22

申请号：US189235

申请日：1998-11-10

申请人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

发明人： H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Derick J. Wristers

IPC分类号： H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  Y10S257/90

摘要： An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.

摘要翻译： 形成集成电路，其中NMOS晶体管的结形成为不同于PMOS晶体管的结。 NMOS晶体管包括LDD区域，MDD区域和重的浓度源极/漏极区域。 相反，PMOS晶体管包括LDD区域和源极/漏极区域。 NMOS晶体管结形成为不同于PMOS晶体管结，以考虑到相掺杂剂相对于PMOS掺杂剂的移动性较小。 因此，LDD面积的减小和包含MDD面积在NMOS器件中提供更低的源极/漏极电阻和更高的欧姆连接性。 PMOS结包括相对较大的LDD面积，以便将高度移动的，高浓度的硼原子从PMOS沟道拉出。

公开(公告)号：US6103559A

公开(公告)日：2000-08-15

申请号：US282033

申请日：1999-03-30

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/51 ,  H01L21/338 ,  H01L21/3205

CPC分类号： H01L21/28194 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0688 ,  H01L29/517 ,  H01L29/6659 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/66545

摘要： A method is provided for fabricating a semiconductor device, the method including forming a first dielectric layer above a structure and forming an island of a sacrificial layer above the first dielectric layer. The method also includes introducing a first dopant into first portions of the structure, leaving a second portion of the structure protected by the island, and removing first portions of the island leaving a second portion of the island. The method further includes introducing a second dopant into the first portions and third portions of the structure, leaving a fourth portion of the structure protected by the second portion of the island. The method additionally includes forming a second dielectric layer adjacent the second portion of the island, removing the second portion of the island, forming a gate dielectric above the fourth portion of the structure and forming a gate conductor above the gate dielectric.

摘要翻译： 提供了一种用于制造半导体器件的方法，所述方法包括在结构之上形成第一介电层，并在第一介电层上形成牺牲层的岛。 该方法还包括将第一掺杂剂引入到结构的第一部分中，留下由岛保护的结构的第二部分，以及去除离开岛的第二部分的岛的第一部分。 该方法还包括将第二掺杂剂引入到结构的第一部分和第三部分中，留下结构的第四部分被岛的第二部分保护。 该方法还包括形成与岛的第二部分相邻的第二电介质层，去除岛的第二部分，在结构的第四部分之上形成栅极电介质，并在栅极电介质上方形成栅极导体。

公开(公告)号：US6018179A

公开(公告)日：2000-01-25

申请号：US187028

申请日：1998-11-05

申请人： Mark I. Gardner ,  Fred N. Hause ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Fred N. Hause ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/321 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L27/088

CPC分类号： H01L21/28194 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/28202 ,  H01L21/31116 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66583 ,  H01L29/6659 ,  H01L21/3212 ,  Y10S257/90

摘要： A high speed MOS device has a scaled channel length and integrated spacers. The MOS device is formed on a substrate having active and isolation regions. In constructing the MOS device wells and Vt regions are formed as required. Then, a thin nitride layer is formed upon the substrate. Subsequently, an oxide layer is formed upon the nitride layer. Then, the oxide layer is pattern masked to expose gate regions. The gate regions are sloped etched to form slope etched voids. The slope etching may proceed to the nitride layer, through a portion of the nitride layer or fully through the nitride layer, depending upon the embodiment. In another embodiment, the nitride layer is not deposed and the oxide layer is either fully or partially slope etched to the silicon substrate. The patterned mask is then removed and remaining portions of the nitride layer may be converted to an oxynitride. Additionally, a gate oxide may be formed. The slope etched void is then filled with a gate conductor and the surface is planarized in a CMP process. The gate conductor then has a shape wherein its lower surface is smaller than its upper surface. Then, the substrate is isotropically etched to remove portions of the oxide layer and nitride layer unprotected by the gate conductor. The remaining structure includes integrally formed spacers. Active regions, LDD regions and punchthrough regions are then formed to complete formation of the transistor.

摘要翻译： 高速MOS器件具有缩放的沟道长度和集成间隔物。 MOS器件形成在具有有源和隔离区域的衬底上。 在构建MOS器件时，根据需要形成Vt区域。 然后，在基板上形成薄的氮化物层。 随后，在氮化物层上形成氧化物层。 然后，将氧化层图案掩模以露出栅极区域。 栅极区被倾斜蚀刻以形成斜坡蚀刻的空隙。 根据实施例，倾斜蚀刻可以通过氮化物层的一部分或完全通过氮化物层而进行到氮化物层。 在另一个实施例中，氮化物层不被沉积，并且氧化物层被完全或部分地倾斜蚀刻到硅衬底。 然后去除图案化掩模，并且可以将氮化物层的剩余部分转化为氮氧化合物。 另外，可以形成栅极氧化物。 然后用栅极导体填充斜面蚀刻的空隙，并且在CMP工艺中平坦化表面。 然后，栅极导体具有其下表面小于其上表面的形状。 然后，各向同性蚀刻衬底，以除去未被栅极导体保护的氧化物层和氮化物层的部分。 其余结构包括一体形成的间隔物。 然后形成有源区，LDD区和穿透区，以完成晶体管的形成。

公开(公告)号：US5994193A

公开(公告)日：1999-11-30

申请号：US95088

申请日：1998-06-10

申请人： Mark I. Gardner ,  Derick J. Wristers ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Derick J. Wristers ,  Jon D. Cheek

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/28061 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

摘要： An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.

摘要翻译： 提供集成电路晶体管及其制造方法。 晶体管包括衬底，第一和第二源极/漏极区域以及耦合到衬底的栅电极堆叠。 通过在基板上形成第一绝缘层，在第一绝缘层上形成第一导体层，在第一导体层上形成金属层，制作栅电极堆叠。 诸如层间电介质层的第二绝缘层耦合到与栅电极堆叠相邻的衬底。 可以并入侧壁间隔物和LDD处理。 晶体管和方法将金属和多晶硅集成到自对准栅极电极堆叠中。

公开(公告)号：US5891787A

公开(公告)日：1999-04-06

申请号：US923181

申请日：1997-09-04

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76237

摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 .ANG.. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted into regions of the active areas in close proximity to the trench isolation structure.

摘要翻译： 一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。 该方法包括在半导体衬底上形成电介质掩模层。 然后通过掩模层形成开口。 在开口内的掩模层的侧壁上形成一对电介质隔离物。 然后在电介质间隔物之间​​的半导体衬底中蚀刻沟槽。 然后在沟槽的壁和基底上热生长第一介电层。 将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。 间隔物的部分也被去除，使得间隔物的厚度在约0至200安培之间。 然后将硅原子和/或势垒原子（例如氮原子）注入紧邻沟槽隔离结构的有源区的区域中。