公开(公告)号：US20110002172A1

公开(公告)日：2011-01-06

申请号：US12728694

申请日：2010-03-22

申请人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/02 ,  G11C11/34

CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3409 ,  G11C16/3413 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; a inner insulating film provided between the memory layer and the semiconductor pillar; a outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.

摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括多层结构，其包括沿第一方向交替堆叠的电极膜和电极间绝缘膜; 在所述第一方向上穿透所述多层结构的半导体柱; 设置在所述半导体柱和所述电极膜之间的存储层; 设置在所述存储层和所述半导体柱之间的内部绝缘膜; 设置在存储层和电极膜之间的外部绝缘膜; 以及电连接到第一半导体柱的布线。 在擦除操作中，控制单元将第一布线设置在第一电位，并将电极膜设置在比第一电位低的第二电位，然后将第一布线设置在第三电位，并将电极膜设置为高于第四电位 比第三个潜力。

公开(公告)号：US20100327339A1

公开(公告)日：2010-12-30

申请号：US12728727

申请日：2010-03-22

申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.

摘要翻译： 一种设置有单元阵列部分和外围电路部分的半导体存储器件，该器件包括：背栅电极; 设置在所述背栅电极上的层叠体; 沿层叠方向延伸的多个半导体柱; 连接构件，每个连接构件将半导体柱之一连接到另一个半导体柱; 向所述背栅电极施加电位的背栅极电极接触; 设置在所述外围电路部中的栅电极; 以及向所述栅电极，所述背栅电极和所述栅电极施加电位的栅电极接触部，分别包括：下半导体层; 设置在下半导体层上的导电层; 以及设置在所述导电层上的上半导体层，所述连接构件设置在所述上​​半导体层中或所述上半导体层上，所述背栅电极接触和所述栅电极接触与所述导电层接触。

公开(公告)号：US20100244119A1

公开(公告)日：2010-09-30

申请号：US12724713

申请日：2010-03-16

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L21/223 ,  H01L21/265 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于 第一方向 第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。

公开(公告)号：US20100213538A1

公开(公告)日：2010-08-26

申请号：US12709702

申请日：2010-02-22

申请人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11582

摘要： A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium.

摘要翻译： 存储器串包括：第一半导体层，具有相对于衬底在垂直方向上延伸的多个柱状部分，以及连接多个柱状部分的下端的接合部分; 围绕所述第一半导体层的侧表面的电荷存储层; 以及围绕电荷存储层的侧表面并用作存储单元的控制电极的第一导电层。 选择晶体管包括：从柱状部分的上表面向上延伸的第二半导体层; 围绕所述第二半导体层的侧表面的绝缘层; 围绕所述绝缘层的侧表面并用作所述选择晶体管的控制电极的第二导电层; 以及形成在所述第二半导体层的上表面上并且包括硅锗的第三半导体层。

公开(公告)号：US20100213537A1

公开(公告)日：2010-08-26

申请号：US12708161

申请日：2010-02-18

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/8239

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A memory string comprises: a pair of columnar portions; a first insulating layer surrounding a side surface of the columnar portions; a charge storage layer surrounding a side surface of the first insulating layer; a second insulating layer surrounding a side surface of the charge storage layer; and a first conductive layer surrounding a side surface of the second insulating layer. A select transistor comprises: a second semiconductor layer extending from an upper surface of the columnar portions; a third insulating layer surrounding a side surface of the second semiconductor layer; a fourth insulating layer surrounding a side surface of the third insulating layer; and a second conductive layer surrounding a side surface of the fourth insulating layer. The first semiconductor layer is formed continuously in an integrated manner with the second semiconductor layer. The first insulating layer is formed continuously in an integrated manner with the third insulating layer.

摘要翻译： 存储器串包括：一对柱状部分; 围绕所述柱状部分的侧表面的第一绝缘层; 围绕所述第一绝缘层的侧表面的电荷存储层; 围绕电荷存储层的侧表面的第二绝缘层; 以及围绕所述第二绝缘层的侧表面的第一导电层。 选择晶体管包括：从柱状部分的上表面延伸的第二半导体层; 围绕所述第二半导体层的侧表面的第三绝缘层; 围绕所述第三绝缘层的侧表面的第四绝缘层; 以及围绕所述第四绝缘层的侧表面的第二导电层。 第一半导体层以与第二半导体层一体化的方式连续地形成。 第一绝缘层与第三绝缘层一体地形成。

公开(公告)号：US20100207193A1

公开(公告)日：2010-08-19

申请号：US12705088

申请日：2010-02-12

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582

摘要： A plurality of a first conductive layers are provided at a certain interval L in a vertical direction, with a dielectric sandwiched therebetween. The certain interval L is set so that the first dielectric has an equivalent oxide thickness DEOT that satisfies the following relation (1). Dsio2

摘要翻译： 多个第一导电层在垂直方向上以一定间隔L设置，夹在其间的电介质。 设定一定间隔L使得第一电介质具有满足以下关系式（1）的等效氧化物厚度DEOT。 Dsio2

公开(公告)号：US20100181612A1

公开(公告)日：2010-07-22

申请号：US12638480

申请日：2009-12-15

申请人： Masaru Kito ,  Masaru Kidoh ,  Tomoko Fujiwara ,  Yosuke Komori ,  Megumi Ishiduki ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

发明人： Masaru Kito ,  Masaru Kidoh ,  Tomoko Fujiwara ,  Yosuke Komori ,  Megumi Ishiduki ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

IPC分类号： H01L29/788 ,  H01L21/205 ,  H01L21/336

CPC分类号： H01L29/788 ,  G11C16/0458 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1156 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

摘要： A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole.

摘要翻译： 非易失性半导体存储器件包括：通过交替堆叠多个层间绝缘膜和多个控制栅电极来形成堆叠体; 在层叠体中形成沿堆叠方向延伸的通孔; 通过通孔蚀刻面向通孔的层间绝缘膜的一部分以除去该部分; 形成去除部分; 在通孔的内表面和除去层间绝缘膜的部分之间形成第一绝缘膜; 在除去层间绝缘膜的部分中形成浮栅电极; 形成第二绝缘膜，以覆盖面对通孔的浮栅电极的一部分; 并将半导体柱埋在通孔中。

公开(公告)号：US20100148237A1

公开(公告)日：2010-06-17

申请号：US12555320

申请日：2009-09-08

申请人： Masaru KITO ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

发明人： Masaru KITO ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

IPC分类号： H01L29/788 ,  H01L21/4763

CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

公开(公告)号：US20100109071A1

公开(公告)日：2010-05-06

申请号：US12562781

申请日：2009-09-18

申请人： Hiroyasu TANAKA ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

发明人： Hiroyasu TANAKA ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer. The stacked body in a memory cell array region including a plurality of memory strings is divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, the memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the block is surrounded by the slits formed in a closed pattern.

摘要翻译： 半导体存储器件包括：半导体衬底; 具有交替堆叠的多个导电层和多个电介质层的层叠体，所述层叠体设置在所述半导体基板上; 设置在通过所述层叠体形成的孔内的半导体层，所述半导体层沿所述导电层和所述电介质层的堆叠方向延伸; 以及设置在导电层和半导体层之间的电荷存储层。 包含多个存储器串的存储单元阵列区域中的堆叠体被埋置在其中的层间电介质膜的狭缝分成多个块，该存储串包括在堆叠方向上串联连接的存储单元作为导电 存储单元包括导电层，半导体层和设置在导电层和半导体层之间的电荷存储层，并且每个块被形成为封闭图案的狭缝包围。

公开(公告)号：US20100013049A1

公开(公告)日：2010-01-21

申请号：US12504959

申请日：2009-07-17

申请人： Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Yasuyuki Matsuoka

IPC分类号： H01L23/522 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L27/11578 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first multilayer body is formed by alternately layering dielectric films and electrode films on a substrate. Then, an end portion of the first multilayer body is processed into a staircase shape, and a first interlayer dielectric film is formed around the first multilayer body. Next, a plurality of contact holes having a diameter decreasing downward are formed in the first interlayer dielectric film so that the contact holes reach respective end portions of the electrode films. Then, a sacrificial material is buried in the contact holes. Next, a second multilayer body is formed immediately above the first multilayer body, and a second interlayer dielectric film is formed around the second multilayer body. Thereafter, a plurality of contact holes having a diameter decreasing downward are formed in the second interlayer dielectric film to communicate with the respective contact holes formed in the first interlayer dielectric film. Then, the sacrificial material is removed and a contact is buried inside the contact holes. The contact has a step difference.

摘要翻译： 通过在基板上交替层叠电介质膜和电极膜来形成第一多层体。 然后，将第一多层体的端部加工成阶梯状，在第一层叠体的周围形成第一层间绝缘膜。 接下来，在第一层间电介质膜中形成直径减小的多个接触孔，使得接触孔到达电极膜的各个端部。 然后，牺牲材料被埋在接触孔中。 接着，在第一多层体的正上方形成第二层叠体，在第二层叠体的周围形成第二层间绝缘膜。 此后，在第二层间电介质膜中形成直径减小的多个接触孔，与形成在第一层间绝缘膜中的各接触孔连通。 然后，去除牺牲材料并将接触件埋在接触孔内。 联系人有差异。