公开(公告)号：US20240284672A1

公开(公告)日：2024-08-22

申请号：US18443013

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Matthew J. King ,  Indra V. Chary ,  Yoshiaki Fukuzumi ,  Lifang Xu ,  Paolo Tessariol ,  Shuangqiang Luo

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: Methods, systems, and devices for merged cavities for conductor formation in a memory die are described. An array of cavities may be formed through a stack of material layers of a memory die, and conductors may be formed at least in part by merging some of the cavities of the array. Such cavities may be sized in accordance with a relatively smallest feature that implements a subset of such cavities, and a smallest associated feature may be formed using a first subset of the array of cavities. Conductors may be formed at least in part by merging two or more cavities of a second subset of the array of cavities using a material removal operation to remove portions of the stack of material layers. Such merging may support conductors being formed with a cross-section that is greater than a cross-section of other features formed using such cavities that are not merged.

公开(公告)号：US20240071918A1

公开(公告)日：2024-02-29

申请号：US17822421

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Sidhartha Gupta ,  Indra V. Chary ,  Richard J. Hill ,  Umberto Maria Meotto

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5283 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A microelectronic device includes a stack structure having tiers each including conductive material vertically neighboring insulative material and conductive contact structures. The stack structure is divided into blocks horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction by insulative slot structures. At least one of the blocks includes a lower stadium structure having steps including edges of some of the tiers, and an upper stadium structure vertically overlying the lower stadium structure and having additional steps including edges of some other of the tiers vertically overlying the some of the tiers. The additional steps have greater tread widths in the first direction than the steps. Conductive contact structures are in contact with the additional steps of the upper stadium structure of the at least one of the blocks. Memory devices and electronic systems are also described.

公开(公告)号：US11901292B2

公开(公告)日：2024-02-13

申请号：US17819019

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises an upper portion having a first width, and a lower portion vertically interposed between the upper portion and the contact structures. The lower portion has a tapered profile defining additional widths varying from a second width less than the first width at an uppermost boundary of the lower portion to a third width less than the second width at a lowermost boundary of the lower portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20230403849A1

公开(公告)日：2023-12-14

申请号：US18366748

申请日：2023-08-08

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

公开(公告)号：US11723196B2

公开(公告)日：2023-08-08

申请号：US17063101

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

公开(公告)号：US20230164991A1

公开(公告)日：2023-05-25

申请号：US18094906

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/306 ,  G11C16/04 ,  G11C5/02 ,  H10B43/27 ,  H10B43/30

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/30625 ,  G11C16/0408 ,  G11C16/0466 ,  G11C5/025 ,  H10B43/27 ,  H10B43/30

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230143406A1

公开(公告)日：2023-05-11

申请号：US18083412

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76816 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US11637178B2

公开(公告)日：2023-04-25

申请号：US17078755

申请日：2020-10-23

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Harsh Narendrakumar Jain

IPC: H01L29/06 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230009880A1

公开(公告)日：2023-01-12

申请号：US17373121

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  David H. Wells ,  Harsh Narendrakumar Jain ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

公开(公告)号：US20220216224A1

公开(公告)日：2022-07-07

申请号：US17142804

申请日：2021-01-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu ,  Indra V. Chary

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11573

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the memory regions. A stack extends across the memory regions and the intermediate region. The stack includes alternating conductive levels and insulative levels. Channel-material-pillars are arranged within the memory regions. Memory-block-regions extend longitudinally across the memory regions and the intermediate region. Staircase regions are within the intermediate region. Each of the staircase regions laterally overlaps two of the memory-block-regions. First panel regions extend longitudinally across at least portions of the staircase regions. Second panel regions extend longitudinally and provide lateral separation between adjacent memory-block-regions. The second panel regions are of laterally different dimensions than the first panel regions and/or are compositionally different than the first panel regions. Some embodiments include methods of forming integrated assemblies.