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    Semiconductor memory device
    71.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US06519198B2

    公开(公告)日：2003-02-11

    申请号：US09935010

    申请日：2001-08-21

    申请人： Yasuhiro Suematsu ,  Masaru Koyanagi

    发明人： Yasuhiro Suematsu ,  Masaru Koyanagi

    IPC分类号： G11C700

    CPC分类号： G11C7/12 ,  G11C11/4074 ,  G11C11/4094

    摘要： The bit line overdrive circuit of the present invention comprises a VBLH potential generation circuit generating a bit line final potential relative to a VBLH power supply line for driving a sense amplifier, a charge adjusting capacitance C, a transistor for supplying an overdrive potential to the VBLH power supply line, and a transistor for connecting a PCS node to the VBLH power supply line. The charge pre-charged from the overdrive potential to the VBLH power supply line is shared among the capacitance of the above-noted circuit elements connected to the VBLH power supply line, the bit line capacitance, and the capacitance of a cell capacitor so as to form a VBLH power supply of a substantially one system, thereby avoiding the generation of a power supply noise caused by the power supply switching.

    Semiconductor memory device
    73.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US6069835A

    公开(公告)日：2000-05-30

    申请号：US58218

    申请日：1998-04-10

    申请人： Kenichi Matoba ,  Masaru Koyanagi

    发明人： Kenichi Matoba ,  Masaru Koyanagi

    IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C11/401 ,  H01L27/10 ,  G11C8/00

    CPC分类号： G11C8/12

    摘要： A semiconductor memory device comprises a first core section including a plurality of memory cell arrays, a second core section including a plurality of memory cell arrays and provided below the first core section, a third core section including a plurality of memory cell arrays and provided in a right side of the first core section, and a fourth core section including a plurality of memory cell arrays and provided in a right side of the second core section, wherein at least a part of the memory cell arrays of the first core section and at least a part of the memory cell arrays of the fourth core section are simultaneously activated, and at least a part of the memory cell arrays of the second core section and at least a part of the memory cell arrays of the third core section are simultaneously activated.

    摘要翻译： 半导体存储器件包括：第一芯部分，包括多个存储单元阵列;第二芯部分，包括多个存储单元阵列并且设置在第一芯部下;第三核心部分，包括多个存储单元阵列， 第一芯部的右侧，以及包括多个存储单元阵列并设置在第二芯部的右侧的第四芯部，其中，第一芯部的存储单元阵列的至少一部分和 同时激活第四核心部分的存储单元阵列的至少一部分，并且第二核心部分的至少一部分存储单元阵列和第三核心部分的至少一部分存储单元阵列同时被激活 。

    Constant potential generating circuit and semiconductor device using same
    74.
    发明授权
    Constant potential generating circuit and semiconductor device using same 失效
    恒电位发生电路及使用其的半导体器件

    公开(公告)号：US5880624A

    公开(公告)日：1999-03-09

    申请号：US499514

    申请日：1995-07-07

    申请人： Masaru Koyanagi ,  Kazuhiro Hataoka

    发明人： Masaru Koyanagi ,  Kazuhiro Hataoka

    IPC分类号： H03K17/16

    CPC分类号： H03K17/167

    摘要： When an intermediate potential is required inside a semiconductor device, the constant potential generating circuit can output a stable potential, while maintaining a high driving capability, so that the controllability of the semiconductor device can be improved. The constant potential generating circuit comprises a first output circuit composed of two transistors P16 and N16 for supplying an intermediate output potential V.sub.out to a load; a second output circuit composed of two transistors P11 and N11 for outputting a voltage corresponding to the output potential V.sub.out to a node 13; a resistor R11 interposed between an output point of the output potential V.sub.out and the node 13; and a differential amplifier circuit Ad for comparing the voltage at the node 13 with the reference potential V.sub.ref to apply control signals to the transistors P11, N11, P16 and N16, respectively. In response to the control signals applied from the differential amplifier circuit Ad, the response speed of the second circuit composed of the transistors P11 and N11 is determined higher than that of the first circuit composed of the transistors P16 and N16. Therefore, when the output potential V.sub.out changes relative to the reference potential V.sub.ref, the gate control signals are outputted from the differential amplifier circuit Ad, by comparing the voltage at the node 13 (at which the response speed is high in response to the control signals) with the reference potential V.sub.ref, so that the output potential V.sub.out can be controlled at a stable point at high speed. �FIG. 1!

    摘要翻译： 当在半导体器件内部需要中间电位时，恒定电位产生电路能够在保持高驱动能力的同时输出稳定的电位，从而能够提高半导体器件的可控制性。 恒电位发生电路包括由两个晶体管P16和N16组成的第一输出电路，用于向负载提供中间输出电位Vout; 由两个晶体管P11和N11构成的第二输出电路，用于将与输出电位Vout对应的电压输出到节点13; 插入在输出电位Vout的输出点和节点13之间的电阻器R11; 以及用于将节点13处的电压与参考电位Vref进行比较的差分放大器电路Ad，以将控制信号分别施加到晶体管P11，N11，P16和N16。 响应于从差分放大器电路Ad施加的控制信号，确定由晶体管P11和N11组成的第二电路的响应速度高于由晶体管P16和N16组成的第一电路的响应速度。 因此，当输出电位Vout相对于参考电位Vref变化时，通过比较响应于控制信号的响应速度高的节点13处的电压，从差分放大器电路Ad输出栅极控制信号 ），使得输出电位Vout可以以高速被控制在稳定点。 [图。 1]

    Semiconductor memory device
    75.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5848011A

    公开(公告)日：1998-12-08

    申请号：US824737

    申请日：1997-03-26

    申请人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    发明人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/12

    摘要： A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal. The sense amplifiers can be operated at high speed, while preventing erroneous operation, because the wiring resistances and the parasitic capacitances of the common source node of the sense amplifiers can be reduced.

    摘要翻译： 一种包括存储单元阵列，位线和读出放大器组的半导体存储器件。 存储单元阵列由大致矩阵排列的多个存储单元构成。 响应于行地址解码信号，激活了排成行的多个存储单元。 为每列提供一对位线。 相应的激活的存储器单元的数据被发送到位线对。 读出放大器组中的每一个具有各自连接到位线对的读出放大器的n个单元，以检测和放大读取到与其连接的位线对的数据。 每个读出放大器组的读出放大器的各个参考电位端子连接到单个公共节点，该公共节点可以响应于行地址信号经由读出放大器激活晶体管导通而连接到参考电位。 由于读出放大器的公共源节点的布线电阻和寄生电容可以减小，所以读出放大器可以高速操作，同时防止错误的操作。

    Method of manufacturing a semiconductor device
    76.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US5674763A

    公开(公告)日：1997-10-07

    申请号：US428827

    申请日：1995-04-25

    申请人： Souichi Sugiura ,  Masaru Koyanagi

    发明人： Souichi Sugiura ,  Masaru Koyanagi

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/108 ,  H01L21/265

    CPC分类号： H01L21/823892 ,  H01L27/0922 ,  H01L27/108 ,  Y10S148/035

    摘要： Disclosed herein is a semiconductor device comprising a semiconductor substrate, a well region provided in the surface of the substrate, a plurality of MOSFETs provided in the well region. The well region has parts having a low surface impurity concentration. Some of the MOSFETs have their channel regions provided in those parts of the well region which have the low surface impurity concentration. The other MOSFETs have their channel regions provided in other parts of the well region.

    摘要翻译： 本文公开了一种半导体器件，包括半导体衬底，设置在衬底的表面中的阱区，设置在阱区中的多个MOSFET。 阱区具有表面杂质浓度低的部分。 一些MOSFET在其具有低表面杂质浓度的阱区的那些部分中具有其沟道区。 其它MOSFET的沟道区域设置在阱区的其他部分。

    Semiconductor device having supply voltage deboosting circuit
    77.
    发明授权
    Semiconductor device having supply voltage deboosting circuit 失效
    具有电源电压去抖动电路的半导体器件

    公开(公告)号：US5627493A

    公开(公告)日：1997-05-06

    申请号：US519249

    申请日：1995-08-25

    申请人： Yoshiaki Takeuchi ,  Hiroaki Tanaka ,  Masaru Koyanagi

    发明人： Yoshiaki Takeuchi ,  Hiroaki Tanaka ,  Masaru Koyanagi

    IPC分类号： G05F1/56 ,  G05F1/46 ,  G11C5/00 ,  G11C5/14 ,  G11C11/407 ,  G11C11/408 ,  G11C11/413 ,  H03K19/00 ,  G05F3/02

    CPC分类号： G05F1/465 ,  G11C5/147

    摘要： The semiconductor device comprises: an internal supply voltage deboosting circuit for inputting an external supply voltage, deboosting the inputted external supply voltage, and outputting a deboosted voltage as an internal supply voltage; a first control circuit for deactivating the internal supply voltage deboosting circuit when the external supply voltage is lower than a predetermined value; and a second control circuit for outputting the external supply voltage as the internal supply voltage when the external supply voltage is lower than the predetermined value. When the external supply voltage is lower than a predetermined value, since the internal supply voltage deboosting circuit is deactivated by the first control circuit, the current consumption can be reduced. Further, since the external supply voltage is outputted as the internal supply voltage by the second control circuit, the deboosting operation is not required. The device is usable for different external supply voltages in spite of the same circuit configuration, while preventing the operational margin from being deteriorated.

    摘要翻译： 半导体器件包括：用于输入外部电源电压的内部电源电压去抖动电路，去除所输入的外部电源电压，并输出去激发的电压作为内部电源电压; 第一控制电路，用于当所述外部电源电压低于预定值时停止所述内部电源电压去抖动电路; 以及第二控制电路，用于当外部电源电压低于预定值时输出外部电源电压作为内部电源电压。 当外部电源电压低于预定值时，由于内部电源电压去保护电路被第一控制电路停用，所以可以减少电流消耗。 此外，由于通过第二控制电路输出外部电源电压作为内部电源电压，因此不需要去抖动操作。 尽管有相同的电路配置，该器件可用于不同的外部电源电压，同时防止操作裕度恶化。

    Semiconductor integrated circuit device with data output circuit
    78.
    发明授权
    Semiconductor integrated circuit device with data output circuit 失效
    具有数据输出电路的半导体集成电路器件

    公开(公告)号：US5491430A

    公开(公告)日：1996-02-13

    申请号：US242714

    申请日：1994-05-13

    申请人： Eiichi Makino ,  Masaru Koyanagi

    发明人： Eiichi Makino ,  Masaru Koyanagi

    IPC分类号： G05F1/56 ,  G05F3/24 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/00361

    摘要： The control voltage .phi.1 outputted by the control voltage generating circuit 1 is at a low level in a range where an external supply voltage Vcc is lower than the threshold value of the transistor P1, but increases continuously in analog manner when the external supply voltage Vcc rises. After having matched the external supply voltage Vcc, the control voltage .phi.1 increases in the same way as the external supply voltage Vcc. By use of the control voltage provided with the characteristics as described above for an output circuit, controlled is the gate of a transistor P4 of a low-voltage operating output section 6 operative only at a voltage lower than a predetermined value. The transistor P2 of a full-voltage operating output section 5 of the output circuit is always operative on the basis of the control signal .phi.H of the data output control circuit 3. When the external supply voltage is low below the predetermined value, the transistor P4 is perfectly turned on, so that the conductance thereof increases. In the semiconductor integrated circuit device operative on the basis of a plurality of supply voltages, it is possible to prevent the operation margin from being reduced near the switching point of the gate voltages of the driving transistors and the data output transistors.

    摘要翻译： 控制电压产生电路1输出的控制电压phi 1在外部电源电压Vcc低于晶体管P1的阈值的范围内处于低电平，但是当外部电源电压Vcc 上升。 在匹配外部电源电压Vcc之后，控制电压phi 1以与外部电源电压Vcc相同的方式增加。 通过使用具有如上所述的用于输出电路的特性的控制电压，受控的是低电压工作输出部分6的晶体管P4的栅极仅在低于预定值的电压下工作。 输出电路的全压工作输出部分5的晶体管P2总是基于数据输出控制电路3的控制信号phi H而工作。当外部电源电压低于预定值时，晶体管 P4完全打开，使其电导增加。 在基于多个电源电压工作的半导体集成电路装置中，可以防止在驱动晶体管和数据输出晶体管的栅极电压的切换点附近的操作余量减小。

    Semiconductor integrated circuit
    79.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US5402018A

    公开(公告)日：1995-03-28

    申请号：US107143

    申请日：1993-08-17

    申请人： Masaru Koyanagi

    发明人： Masaru Koyanagi

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/00 ,  H01L21/82 ,  H03K19/08 ,  H03K19/20 ,  H05B37/02

    CPC分类号： G01R31/31701 ,  G06F11/0763 ,  Y10T307/305 ,  Y10T307/359 ,  Y10T307/391 ,  Y10T307/414 ,  Y10T307/461 ,  Y10T307/76

    摘要： A semiconductor integrated circuit is operative in a plurality of different modes. A plurality of select signals whose number corresponds to modes selected from a plurality of different modes are outputted. In response to the select signals, it is detected whether at least two operation modes are selected simultaneously. If so, a detection signal is outputted. In response to this detection signal, the operation of the semiconductor integrated circuit is stopped. Further, in response to the select signal, the semiconductor integrated circuit is activated in a mode by means of a predetermined select signal of these select signals. Further, in response to these select signals, the selected mode can be detected.

    摘要翻译： 半导体集成电路以多种不同的模式工作。 输出对应于从多个不同模式中选择的模式的多个选择信号。 响应于选择信号，检测是否同时选择至少两种操作模式。 如果是，则输出检测信号。 响应该检测信号，停止半导体集成电路的动作。 此外，响应于选择信号，半导体集成电路通过这些选择信号的预定选择信号以模式被激活。 此外，响应于这些选择信号，可以检测所选择的模式。

    Dynamic random access memory
    80.
    发明授权
    Dynamic random access memory 失效
    动态随机存取存储器

    公开(公告)号：US5282167A

    公开(公告)日：1994-01-25

    申请号：US813674

    申请日：1991-12-26

    申请人： Hiroaki Tanaka ,  Masaru Koyanagi

    发明人： Hiroaki Tanaka ,  Masaru Koyanagi

    IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  G11C7/02

    CPC分类号： G11C29/50 ,  G11C11/4085 ,  G11C11/401

    摘要： A DRAM according to the invention has noise-eliminating circuits. Each of the circuits has an output side thereof connected to a corresponding word line. At the time of a voltage stress examination, each of the circuits is controlled to be in an on-state thereby transmitting a voltage stress, input an input side thereof, to the word line. At the time of normal operation, the input side of the circuit is connected to an earth node, and each of the circuits is turned on and off in accordance with a signal output from a corresponding one of word line-selecting circuits or with the level of a corresponding one of the word lines.

    摘要翻译： 根据本发明的DRAM具有消噪电路。 每个电路的输出侧连接到相应的字线。 在电压胁迫检查时，每个电路被控制为导通状态，从而将电压应力传输到字线。 在正常操作时，电路的输入端连接到接地节点，并且每个电路根据从相应的一个字线选择电路输出的信号或者与电平 对应的一行字线。