公开(公告)号：US07470953B2

公开(公告)日：2008-12-30

申请号：US10573793

申请日：2004-10-06

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Akira Kuroyanagi ,  Yasushi Okura ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Akira Kuroyanagi ,  Yasushi Okura ,  Norihito Tokura

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811

摘要： The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P− body region 41, and N− drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.

摘要翻译： 本发明旨在提供可以容易地制造的绝缘栅型半导体器件及其制造方法，同时实现更高的耐压设计和较低的导通电阻设计。 半导体器件包括N +源极区31，N +漏极区11，P-体区41和N漂移区12.通过挖掘半导体器件的上侧的一部分，形成栅沟槽21。 栅极沟槽21包含栅电极22.P浮动区51设置在栅极沟槽21的下方。可以形成与栅极沟槽21的深度不同的另外的沟槽35，设置在沟槽25下方的P浮动区域54。

公开(公告)号：US07456484B2

公开(公告)日：2008-11-25

申请号：US11648894

申请日：2007-01-03

申请人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

发明人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

IPC分类号： H01L21/00

CPC分类号： H01L29/7395 ,  H01L27/0664 ,  H01L29/0834 ,  H01L29/66333 ,  H01L29/861

摘要： A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.

摘要翻译： 半导体器件包括：具有第一和第二半导体层的半导体衬底; IGBT，其具有集电极区域，第一半导体层中的基极区域，基极区域中的发射极区域和发射极区域与第一半导体层之间的基极区域中的沟道区域; 在所述第一半导体层中具有阳极区域的二极管和所述第一半导体层上的阴极电极; 和电阻区域。 集电极区域和第二半导体层设置在第一半导体层上。 用于增加第二半导体层的电阻的电阻区域通过绕过集电极区域而被布置在通过第一半导体层和第二半导体层的沟道区域和阴极电极之间的电流通路中。

公开(公告)号：US20070158680A1

公开(公告)日：2007-07-12

申请号：US11648894

申请日：2007-01-03

申请人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

发明人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

IPC分类号： H01L29/74

CPC分类号： H01L29/7395 ,  H01L27/0664 ,  H01L29/0834 ,  H01L29/66333 ,  H01L29/861

摘要： A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.

摘要翻译： 半导体器件包括：具有第一和第二半导体层的半导体衬底; IGBT，其具有集电极区域，第一半导体层中的基极区域，基极区域中的发射极区域和发射极区域与第一半导体层之间的基极区域中的沟道区域; 在所述第一半导体层中具有阳极区域和在所述第一半导体层上的阴极电极的二极管; 和电阻区域。 集电极区域和第二半导体层设置在第一半导体层上。 用于增加第二半导体层的电阻的电阻区域通过绕过集电极区域而被布置在通过第一半导体层和第二半导体层的沟道区域和阴极电极之间的电流通路中。

公开(公告)号：US06982459B2

公开(公告)日：2006-01-03

申请号：US10634819

申请日：2003-08-06

申请人： Takashi Suzuki ,  Tsutomu Uesugi ,  Norihito Tokura

发明人： Takashi Suzuki ,  Tsutomu Uesugi ,  Norihito Tokura

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/7813

摘要： A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

摘要翻译： 垂直型MOS场效应晶体管在源电极和N + +型漏极区之间具有超结结构。 超结结构由多个P型单晶硅区域和多个N型单晶硅区域构成。 多个P型单晶硅区域和多个N型单晶硅区域中的每一个交替排列。 超结具有两部分，即设置MOS结构的电池形成区域和位于电池形成区域周边的周边区域。 源电极接触周边区域中的P型单晶硅区域中的一个，同时远离位于周边区域中最外侧的周边区域的端部设置。

公开(公告)号：US06639260B2

公开(公告)日：2003-10-28

申请号：US10015917

申请日：2001-12-17

申请人： Takashi Suzuki ,  Tsutomu Uesugi ,  Norihito Tokura

发明人： Takashi Suzuki ,  Tsutomu Uesugi ,  Norihito Tokura

IPC分类号： H01L2976

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/7813

摘要： A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

摘要翻译： 垂直型MOS场效应晶体管在源电极和N +型漏极区之间具有超结结构。 超结结构由多个P型单晶硅区域和多个N型单晶硅区域构成。 多个P型单晶硅区域和多个N型单晶硅区域中的每一个交替排列。 超结具有两部分，即设置MOS结构的电池形成区域和位于电池形成区域周边的周边区域。 源电极接触周边区域中的P型单晶硅区域中的一个，同时远离位于周边区域中最外侧的周边区域的端部设置。

公开(公告)号：US5976936A

公开(公告)日：1999-11-02

申请号：US893221

申请日：1997-07-15

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

IPC分类号： H01L21/04 ,  H01L29/08 ,  H01L29/24 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66068 ,  H01L29/7828 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4236 ,  Y10S438/981

摘要： A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9.

摘要翻译： 提供了具有高阻断电压，低损耗和低阈值电压的碳化硅半导体器件。 n +型碳化硅半导体衬底1，n型碳化硅半导体衬底2和p型碳化硅半导体层3相互层叠在一起。 在p型碳化硅半导体层3的表面的预定区域中形成n +型源极区6，并且形成沟槽9，以延伸穿过n +型源极区6和p型碳化硅半导体层 在n型碳化硅半导体层2的表面上延伸设置有薄膜半导体层（n型或p型）11a，在n +型源极区6，p型碳化硅半导体层3的表面上， n型碳化硅半导体层2在沟槽9的侧面。

公开(公告)号：US5780953A

公开(公告)日：1998-07-14

申请号：US658532

申请日：1996-06-05

申请人： Atsushi Umeda ,  Norihito Tokura ,  Hirohide Sato ,  Makoto Taniguchi ,  Shin Kusase

发明人： Atsushi Umeda ,  Norihito Tokura ,  Hirohide Sato ,  Makoto Taniguchi ,  Shin Kusase

IPC分类号： H02J7/14 ,  H02K1/22 ,  H02K11/04 ,  H02K21/00 ,  H02K21/04 ,  H02P9/48

CPC分类号： H02P9/48 ,  H02J7/1492 ,  H02K11/046 ,  H02K21/044 ,  Y02T10/92

摘要： In an on-vehicle alternator, both the magnetic flux variation frequency and maximum flux density are decreased sufficiently to thereby decrease the internal iron loss and thereby realize an increase in the current generation efficiency. The on-vehicle alternator comprises a rotor wherein magnetic pole cores that are polarized by a rotor coil to alternately different polarities are circumferentially disposed on the outer periphery thereof at prescribed equi-angular intervals. A permanent magnet which is embedded within a resin-made retainer body is provided between the magnetic pole cores and has side faces, as viewed circumferentially, which are polarized respectively to the same polarities as those of adjacent respective magnetic pole cores to thereby vary the magnetic flux quantity directed toward stator coils so as to exhibit a circumferential gentle curve. A rectifier is constructed using SiC-MOS transistors so that it is conductive and operative to thereby charge a battery with the current developed in the stator coils only when the alternating current voltages generated in the stator coils have become higher than the battery voltage.

摘要翻译： 在车载交流发电机中，磁通量变化频率和最大磁通密度都充分降低，从而降低内部铁损，从而实现电流产生效率的提高。 车载交流发电机包括转子，其中由转子线圈极化为交替不同极性的磁极铁芯以规定的等角间隔周向地设置在其外周。 嵌入在树脂制保持器本体内的永磁体设置在磁极芯之间，并且具有圆周方向的侧面，其分别极化到与相邻的各个磁极芯的极性相同的极性，从而改变磁性 磁通量定向于定子线圈，以便呈现圆周平缓曲线。 使用SiC-MOS晶体管构造整流器，使得它是导电的并且可操作，从而仅当在定子线圈中产生的交流电压变得高于电池电压时，才能利用定子线圈中产生的电流对电池充电。

公开(公告)号：US5753943A

公开(公告)日：1998-05-19

申请号：US612285

申请日：1996-03-07

申请人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

发明人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/322 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/749

CPC分类号： H01L29/66333 ,  H01L21/3221 ,  H01L29/0834 ,  H01L29/7395 ,  Y10S257/913

摘要： In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

公开(公告)号：US5723376A

公开(公告)日：1998-03-03

申请号：US745958

申请日：1996-11-07

申请人： Yuuichi Takeuchi ,  Takeshi Miyajima ,  Kazukuni Hara ,  Norihito Tokura

发明人： Yuuichi Takeuchi ,  Takeshi Miyajima ,  Kazukuni Hara ,  Norihito Tokura

IPC分类号： H01L21/04 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L29/7813 ,  H01L21/049 ,  H01L29/42368 ,  H01L29/66068 ,  Y10S438/931

摘要： A groove is formed on the surface of a semiconductor substrate composed of silicon carbide and a first thermal oxidation film is formed by executing thermal oxidation on a damaged layer of groove inner walls. Then, the first thermal oxidation film is removed so that the damaged layer can be removed. Since a second thermal oxidation film is formed after the damaged layer is removed, the second thermal oxidation film is uniform. A silicon carbide semiconductor device can be achieved with less side etching because substantially a (0001) carbon face of a cubic system is chosen as the plane orientation of the semiconductor substrate.

摘要翻译： 在由碳化硅构成的半导体基板的表面上形成有槽，通过对凹槽内壁的损伤层进行热氧化而形成第一热氧化膜。 然后，去除第一热氧化膜，从而可以去除损伤层。 由于在损坏层被去除之后形成第二热氧化膜，所以第二热氧化膜是均匀的。 可以通过较少的侧面蚀刻实现碳化硅半导体器件，因为基本上选择立方晶系的（0001）碳面作为半导体衬底的平面取向。

公开(公告)号：US4739183A

公开(公告)日：1988-04-19

申请号：US888805

申请日：1986-07-24

申请人： Norihito Tokura ,  Hisasi Kawai

发明人： Norihito Tokura ,  Hisasi Kawai

IPC分类号： B60R16/02 ,  B60R16/03 ,  B60Q1/00

CPC分类号： B60R16/0315 ,  B60R2016/0322 ,  Y10S370/908 ,  Y10T307/484

摘要： Disclosed is a local area network for a vehicle which comprises a plurality of terminal stations each having an input/output port for various signals, a main-loop formed by series connection of the terminal stations and transmission lines, a sub-loop arranged in parallel to the main-loop and formed by series connection of the terminal stations and transmission lines, and controllers. One of the terminal stations receives a large amount of information such as an audio signal from an audio transmitter and one of the other terminal stations supplies a large amount of information such as an audio signal to an audio receiver. When the main-loop is in a normal operation state, the main-loop operates as a token-passing system and the sub-loop acts as a direct transmission route from one of the terminal stations to another terminal station, and when the main-loop is in an abnormal operation state, the main-loop is coupled with the sub-loop and the transmitting of information such as an audio signal is stopped, and simultaneously, the sub-loop is switched to the token-passing system. Thus, the double loops, i.e., the main-loop and the sub-loop, are effectively utilized. In addition, any decrease in the reliability of various signals transmission when a failure of the main-loop occurs, can be prevented.

摘要翻译： 公开了一种用于车辆的局域网，其包括多个终端站，每个终端站具有用于各种信号的输入/输出端口，通过终端站和传输线的串联连接形成的主回路，并行布置的子回路 到主回路并由终端站和传输线以及控制器的串联连接形成。 一个终端站接收来自音频发送器的大量信息，例如音频信号，另一个终端站之一向音频接收机提供诸如音频信号的大量信息。 当主回路处于正常运行状态时，主回路作为令牌传递系统运行，子回路作为从终端站到另一个终端站的直接传输路由， 环路处于异常操作状态，主回路与子回路耦合，并且停止诸如音频信号的信息的发送，并且同时将子回路切换到令牌传递系统。 因此，有效地利用了双回路，即主回路和子回路。 此外，可以防止发生主回路故障时各种信号传输的可靠性的任何降低。