公开(公告)号：US06982459B2

公开(公告)日：2006-01-03

申请号：US10634819

申请日：2003-08-06

申请人： Takashi Suzuki ,  Tsutomu Uesugi ,  Norihito Tokura

发明人： Takashi Suzuki ,  Tsutomu Uesugi ,  Norihito Tokura

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/7813

摘要： A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

摘要翻译： 垂直型MOS场效应晶体管在源电极和N + +型漏极区之间具有超结结构。 超结结构由多个P型单晶硅区域和多个N型单晶硅区域构成。 多个P型单晶硅区域和多个N型单晶硅区域中的每一个交替排列。 超结具有两部分，即设置MOS结构的电池形成区域和位于电池形成区域周边的周边区域。 源电极接触周边区域中的P型单晶硅区域中的一个，同时远离位于周边区域中最外侧的周边区域的端部设置。

公开(公告)号：US06639260B2

公开(公告)日：2003-10-28

申请号：US10015917

申请日：2001-12-17

申请人： Takashi Suzuki ,  Tsutomu Uesugi ,  Norihito Tokura

发明人： Takashi Suzuki ,  Tsutomu Uesugi ,  Norihito Tokura

IPC分类号： H01L2976

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/7813

摘要： A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N+-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

摘要翻译： 垂直型MOS场效应晶体管在源电极和N +型漏极区之间具有超结结构。 超结结构由多个P型单晶硅区域和多个N型单晶硅区域构成。 多个P型单晶硅区域和多个N型单晶硅区域中的每一个交替排列。 超结具有两部分，即设置MOS结构的电池形成区域和位于电池形成区域周边的周边区域。 源电极接触周边区域中的P型单晶硅区域中的一个，同时远离位于周边区域中最外侧的周边区域的端部设置。

公开(公告)号：US20140048911A1

公开(公告)日：2014-02-20

申请号：US14113419

申请日：2012-05-10

申请人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

发明人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

IPC分类号： H01L29/06

CPC分类号： H01L29/063 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/861

摘要： A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.

摘要翻译： 横向半导体器件包括半导体层，绝缘层和电阻场板。 半导体层包括在表面部分处的第一半导体区域和第二半导体区域，并且第二半导体区域在第一半导体区域周围形成电路。 绝缘层形成在半导体层的表面上并且设置在第一和第二半导体区之间。 电阻场板形成在绝缘层的表面上。 在第一和第二半导体区域之间，第一部分和第二部分沿着围绕第一半导体区域的圆周方向彼此相邻。 电阻场板包括分别形成在第一和第二部分中的第一和第二电阻场板部分，并且第一和第二电阻场板部分彼此分离。

公开(公告)号：US08476673B2

公开(公告)日：2013-07-02

申请号：US13296832

申请日：2011-11-15

申请人： Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Shinya Sakurai ,  Takashi Suzuki

发明人： Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Shinya Sakurai ,  Takashi Suzuki

IPC分类号： H01L29/861 ,  H01L29/747 ,  H01L31/107

CPC分类号： H01L21/76283 ,  H01L27/0814 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/405 ,  H01L29/8611

摘要： A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.

摘要翻译： 二极管在半导体层的表面上具有半导体层和阴极和阳极电极。 半导体层具有分别与阴极和阳极电极接触的阴极和阳极区域。 阳极区域具有表面浓度高的第一扩散区域，具有中间表面浓度的第二扩散区域和具有低表面浓度的第三扩散区域。 第一扩散区被第二和第三扩散区覆盖。 第二扩散区域具有面对阴极区域的第一侧表面，与阴极区域相对的第二侧表面和在第一和第二侧表面之间延伸的底表面。 第三扩散区域覆盖连接第一侧表面与底表面的第一角部和将第二侧表面与底表面连接的第二角部中的至少一个。

公开(公告)号：US09240445B2

公开(公告)日：2016-01-19

申请号：US14113419

申请日：2012-05-10

申请人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

发明人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

IPC分类号： H01L23/62 ,  H01L29/06 ,  H01L29/40 ,  H01L29/861

CPC分类号： H01L29/063 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/861

摘要： A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.

摘要翻译： 横向半导体器件包括半导体层，绝缘层和电阻场板。 半导体层包括在表面部分处的第一半导体区域和第二半导体区域，并且第二半导体区域在第一半导体区域周围形成电路。 绝缘层形成在半导体层的表面上并且设置在第一和第二半导体区之间。 电阻场板形成在绝缘层的表面上。 在第一和第二半导体区域之间，第一部分和第二部分沿着围绕第一半导体区域的圆周方向彼此相邻。 电阻场板包括分别形成在第一和第二部分中的第一和第二电阻场板部分，并且第一和第二电阻场板部分彼此分离。

公开(公告)号：US07586151B2

公开(公告)日：2009-09-08

申请号：US11578949

申请日：2005-05-11

申请人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7811

摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.

摘要翻译： 本发明提供了一种绝缘栅半导体器件，其在沟槽底部附近具有浮动区域，并且能够可靠地实现高耐压。 绝缘栅半导体器件100包括电流流过的单元区域和围绕单元区域的端子区域。 半导体器件100还在单元区域中具有多个栅极沟槽21以及端子区域中的多个端子沟槽62。 栅极沟槽21形成为条状，并且端子沟槽62同心地形成。 在半导体器件100中，栅极沟槽21和端子沟槽62以栅极沟槽21的端部和端子沟槽62的侧面之间的间隔均匀的方式定位。 也就是说，栅极沟槽21的长度根据端子沟槽62的拐角的曲率来调节。

公开(公告)号：US20070200138A1

公开(公告)日：2007-08-30

申请号：US11709272

申请日：2007-02-22

申请人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

发明人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

IPC分类号： H01L29/74

CPC分类号： H01L27/0611 ,  H01L29/7395 ,  H01L29/8611

摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.

摘要翻译： 半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。 第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。

公开(公告)号：US6133587A

公开(公告)日：2000-10-17

申请号：US23280

申请日：1998-02-13

申请人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

发明人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/0696

摘要： A n.sup.- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a predetermined region of the surface layer section in the p-type silicon carbide semiconductor layer 3. A trench 7 is formed in a predetermined region in the n.sup.+ -type source region 5, which trench 7 passes through the n.sup.+ -type source region 5 and the p-type silicon carbide semiconductor layer 3, reaching the n.sup.- -type silicon carbide semiconductor layer 2. The trench 7 has side walls 7a perpendicular to the surface of the semiconductor substrate 4 and a bottom side 7b parallel to the surface of the semiconductor substrate 4. The hexagonal region surrounded by the side walls 7a of the trench 7 is an island semiconductor region 12. A high-reliability gate insulating film 8 is obtained by forming a gate insulating layer on the side walls 7a which surround the island semiconductor region 12.

摘要翻译： n型源极区5形成在半导体衬底4的p型碳化硅半导体层3的表层部分的预定区域上。低电阻p型碳化硅区6形成在 在p型碳化硅半导体层3中的表层部分的预定区域。沟槽7形成在n +型源极区域5中的预定区域中，沟槽7通过n +型源极区域5，并且 p型碳化硅半导体层3，到达n型碳化硅半导体层2.沟槽7具有垂直于半导体衬底4的表面的侧壁7a和平行于半导体衬底的表面的底侧7b 由沟槽7的侧壁7a包围的六边形区域是岛状半导体区域12.通过在侧壁7a上形成栅极绝缘层，形成高可靠性栅极绝缘膜8， 岛半导体区域12。

公开(公告)号：US6133120A

公开(公告)日：2000-10-17

申请号：US704820

申请日：1996-08-28

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Atsuo Fukumoto ,  Hidemitsu Hayashi

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Atsuo Fukumoto ,  Hidemitsu Hayashi

IPC分类号： H01L21/205 ,  C30B25/00 ,  C30B25/02 ,  H01L21/04 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  C01B31/36

CPC分类号： H01L29/7813 ,  C30B25/00 ,  C30B25/02 ,  C30B29/36 ,  H01L21/0455 ,  H01L29/66068 ,  H01L29/1608 ,  Y10S438/931

摘要： A p-type silicon carbide semiconductor having a high carrier concentration and activation rate is provided by doping boron as an acceptor impurity in a single crystal silicon carbide. The boron occupies silicon sites in a crystal lattice of the single crystal silicon carbide.

摘要翻译： 通过在单晶碳化硅中掺杂硼作为受主杂质来提供具有高载流子浓度和活化速率的p型碳化硅半导体。 硼占据单晶碳化硅的晶格中的硅位置。

公开(公告)号：US5780324A

公开(公告)日：1998-07-14

申请号：US605637

申请日：1996-02-22

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236

摘要： A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

摘要翻译： 公开了一种具有凹槽结构的垂直DMOSFET的制造方法，其不允许将缺陷或污染物引入通道部分并且可以使凹槽的形状均匀。 在（100）取向的n-on + n外延晶片的表面上，通过化学干蚀刻形成初始槽。 然后通过LOCOS技术将开槽的表面氧化以形成LOCOS氧化物膜，由此在外延晶片上形成凹形结构。 凹形宽度被设定为凹入深度的至少两倍，并且将侧壁角度设定为大约50°以使高通道迁移面的侧壁平面（111）。 在该过程之后，使用LOCOS氧化物膜作为双扩散掩模，从主表面扩散p型和n型杂质，以形成体区和源区。