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公开(公告)号：US20210064788A1
公开(公告)日：2021-03-04
申请号：US16997661
申请日：2020-08-19
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Liji Gopalakrishnan , John Eric Linstadt , Steven C. Woo
Abstract: Methods and systems for enabling secure memory transactions in a memory controller are disclosed. Responsive to determining that an incoming request is for a secure memory transaction, the incoming request is placed in a secure request container. The memory container then enters a state where re-ordering between requests for secure memory transactions placed in the secure request container and requests for non-secure memory transactions from other containers is prevented in a scheduling queue.
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公开(公告)号：US20200351038A1
公开(公告)日：2020-11-05
申请号：US16861164
申请日：2020-04-28
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
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公开(公告)号：US20200073752A1
公开(公告)日：2020-03-05
申请号：US16678159
申请日：2019-11-08
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Craig E. Hampel
Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation
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公开(公告)号：US10523344B2
公开(公告)日：2019-12-31
申请号：US16393817
申请日：2019-04-24
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
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公开(公告)号：US10236051B2
公开(公告)日：2019-03-19
申请号：US15666496
申请日：2017-08-01
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC: G11C11/24 , G11C11/4076 , G11C7/10 , G06F13/16 , G06F13/40 , G11C5/06 , G11C29/02 , G11C29/50 , G11C8/18 , G11C7/22 , G06F1/10 , G11C11/409 , G11C11/4096 , G06F1/06 , G06F1/12 , G06F3/06 , G11C7/04
Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.
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Patent Agency Ranking
公开(公告)号：US20180203759A1
公开(公告)日：2018-07-19
申请号：US15838161
申请日：2017-12-11
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Craig E. Hampel
CPC classification number: G06F11/1004 , G06F11/0703 , G06F11/073 , G06F11/1679 , H03M13/09
Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation
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公开(公告)号：US20180157615A1
公开(公告)日：2018-06-07
申请号：US15813963
申请日：2017-11-15
Applicant: Rambus Inc.
Inventor： Mark A. Horowitz , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
CPC classification number: G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.
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公开(公告)号：US09870283B2
公开(公告)日：2018-01-16
申请号：US14864500
申请日：2015-09-24
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Craig E. Hampel
CPC classification number: G06F11/1004 , G06F11/0703 , G06F11/073 , G06F11/1679 , H03M13/09
Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation
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公开(公告)号：US09667359B2
公开(公告)日：2017-05-30
申请号：US14718019
申请日：2015-05-20
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
CPC classification number: H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
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80.发明授权Method and system for synchronizing address and control signals in threaded memory modules 有权方法和系统，用于在螺纹存储器模块中同步地址和控制信号公开(公告)号：US09507738B2
公开(公告)日：2016-11-29
申请号：US14284473
申请日：2014-05-22
Applicant: Rambus Inc.
Inventor： Arun Vaidyanath , Craig E. Hampel
CPC classification number: G06F13/16 , G06F12/06 , G06F13/1689 , G06F2212/251 , G11C5/04 , G11C5/063 , G11C7/1072 , G11C8/18 , G11C29/023 , G11C29/025 , G11C29/027
Abstract: A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time.
Abstract translation: 存储器系统包括还包括一组存储器件的存储器模块。 该组存储器件包括存储器件的第一子集和存储器件的第二子集。 地址总线设置在存储器模块上，其中地址总线包括耦合到第一子集的第一段和耦合到第二子集的第二段。 地址信号依次遍历该组存储器件。 存储器系统还包括耦合到存储器模块的存储器控制器。 存储器控制器包括第一电路，用于输出控制第一子集的第一控制信号，使得第一控制信号和地址信号在基本上同时到达第一子集中的存储器件。 存储器控制器还包括第二电路，用于输出控制第二子集的第二控制信号，使得第二控制信号和地址信号在基本上同时到达第二子集中的存储器件。
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