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    Split-path equalizer and related methods, devices and systems
    71.
    发明授权
    Split-path equalizer and related methods, devices and systems 有权

    公开(公告)号：US11463283B1

    公开(公告)日：2022-10-04

    申请号：US17073963

    申请日：2020-10-19

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Jared L. Zerbe

    IPC: H04L25/03 ,  H04L7/033 ,  H03L7/00 ,  H03L7/08 ,  H04L25/08 ,  H04L7/00

    Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

    Low-power source-synchronous signaling
    72.
    发明授权
    Low-power source-synchronous signaling 有权

    公开(公告)号：US11195570B2

    公开(公告)日：2021-12-07

    申请号：US16549992

    申请日：2019-08-23

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Frederick A. Ware

    IPC: G06F13/42 ,  G11C11/4076 ,  G06F1/04 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04 ,  G11C29/02 ,  H04L7/00

    Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

    Multi-Mode Clock Multiplier
    75.
    发明申请
    Multi-Mode Clock Multiplier 审中-公开

    公开(公告)号：US20200350918A1

    公开(公告)日：2020-11-05

    申请号：US16813156

    申请日：2020-03-09

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

    IPC: H03L7/16 ,  H03L7/06 ,  H03L7/099 ,  H03K5/00 ,  H03K5/13 ,  H03K3/03 ,  H03K5/14 ,  H03L7/24

    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

    USING A STUTTERED CLOCK SIGNAL TO REDUCE SELF-INDUCED VOLTAGE NOISE
    76.
    发明申请
    USING A STUTTERED CLOCK SIGNAL TO REDUCE SELF-INDUCED VOLTAGE NOISE 审中-公开

    公开(公告)号：US20200042034A1

    公开(公告)日：2020-02-06

    申请号：US16546687

    申请日：2019-08-21

    Applicant: Rambus Inc.

    Inventor： Brian S. Leibowitz ,  Jared L. Zerbe

    IPC: G06F1/12 ,  G06F1/08 ,  G06F1/3237

    Abstract: The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.

    Integrated circuit having a multiplying injection-locked oscillator
    77.
    发明授权
    Integrated circuit having a multiplying injection-locked oscillator 有权

    公开(公告)号：US10404262B2

    公开(公告)日：2019-09-03

    申请号：US15390362

    申请日：2016-12-23

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Barry W. Daly ,  Dustin T. Dunwell ,  Anthony C. Carusone ,  John C. Eble, III

    IPC: H03L7/24 ,  H03K3/03 ,  H03B27/00 ,  H03K5/133 ,  H03K5/156

    Abstract: Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

    Run-time output clock determination
    79.
    发明授权
    Run-time output clock determination 有权

    公开(公告)号：US10205458B2

    公开(公告)日：2019-02-12

    申请号：US15644632

    申请日：2017-07-07

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

    IPC: H03L7/16 ,  H03K3/03 ,  H03K5/00 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/24 ,  H03L7/099

    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

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