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公开(公告)号：US09465751B2
公开(公告)日：2016-10-11
申请号：US13996438
申请日：2012-03-30
申请人： Xiaowei Jiang , Hongliang Gao , Zhen Fang , Srihari Makineni , Ravishankar Iyer
发明人： Xiaowei Jiang , Hongliang Gao , Zhen Fang , Srihari Makineni , Ravishankar Iyer
CPC分类号： G06F12/1466 , G06F12/1027 , G06F12/126
摘要： An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.
摘要翻译： 描述了一种装置，其包含处理核心，其包括CPU核心和耦合到CPU核心的至少一个加速器。 CPU核心包括具有翻译旁边缓冲器的管线。 CPU核心包括逻辑电路，用于在转换后备缓冲器条目中的条目的属性数据中设置锁定位，以锁定为加速器保留的存储器页面。
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72.发明授权Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing 有权包括动态C0状态缓存调整大小的节能和节能的方法，装置和系统公开(公告)号：US08984311B2
公开(公告)日：2015-03-17
申请号：US13341657
申请日：2011-12-30
申请人： Jaideep Moses , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S. R. Degalahal
发明人： Jaideep Moses , Rameshkumar G. Illikkal , Ravishankar Iyer , Jared E. Bendt , Sadagopan Srinivasan , Andrew J. Herdrich , Ashish V. Choubal , Avinash N. Ananthakrishnan , Vijay S. R. Degalahal
CPC分类号： G06F1/3275 , G06F1/3225 , G06F1/3287 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
摘要翻译： 描述了用于设备的能量效率操作的系统，装置和方法的实施例。 在一些实施例中，监视高速缓存的高速缓存性能指示符，并且确定基于高速缓存性能指示符的一个或多个高速缓存性能参数的集合。 基于缓存性能参数与其节能目标的比较来缓存高速缓存大小，以达到最佳高速缓存大小，从而降低功耗。
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公开(公告)号：US08819388B2
公开(公告)日：2014-08-26
申请号：US13550966
申请日：2012-07-17
申请人： Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E. Espig , Ravishankar Iyer
发明人： Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E. Espig , Ravishankar Iyer
CPC分类号： G06F12/1036 , G06F12/0292 , G06F12/0888 , G06F12/10 , G06F12/1027 , G06F2212/206
摘要： Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.
摘要翻译： 描述了用于控制片上系统结构（OSF）块的方法和装置。 在一个实施例中，响应于用户级请求可以存储对应于物理地址的影子地址，并且逻辑电路（例如，存在于OSF中）可以从影子地址确定物理地址。 还公开了其他实施例。
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公开(公告)号：US20140192715A1
公开(公告)日：2014-07-10
申请号：US13993346
申请日：2011-12-30
申请人： Omesh Tickoo , Ravishankar Iyer
发明人： Omesh Tickoo , Ravishankar Iyer
摘要： A route for establishing a wireless connection between a wireless device and a node may be selected based on an estimated duration of the route. The route duration may be estimated based on information related to the expected movement of nodes included in the route.
摘要翻译： 可以基于路由的估计持续时间来选择用于在无线设备和节点之间建立无线连接的路由。 可以基于与路由中包括的节点的预期移动相关的信息来估计路由持续时间。
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公开(公告)号：US08225069B2
公开(公告)日：2012-07-17
申请号：US12415941
申请日：2009-03-31
申请人： Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E Espig , Ravishankar Iyer
发明人： Zhen Fang , Mahesh Wagh , Jasmin Ajanovic , Michael E Espig , Ravishankar Iyer
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/0292 , G06F12/0888 , G06F12/10 , G06F12/1027 , G06F2212/206
摘要： Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.
摘要翻译： 描述了用于控制片上系统结构（OSF）块的方法和装置。 在一个实施例中，响应于用户级请求可以存储对应于物理地址的影子地址，并且逻辑电路（例如，存在于OSF中）可以从影子地址确定物理地址。 还公开了其他实施例。
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公开(公告)号：US20120082387A1
公开(公告)日：2012-04-05
申请号：US12896077
申请日：2010-10-01
IPC分类号： G06K9/46
CPC分类号： G06K9/481 , G06K9/00973 , G06K9/4671 , G06K2009/485
摘要： Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
摘要翻译： 识别图像的方法和系统可以包括具有硬件模块的装置，该硬件模块具有对于图像中的多个向量的逻辑，基于图像矢量的偶数像素确定第一中间计算，并且基于奇数来确定第二中间计算 图像矢量的像素。 逻辑还可以将第一和第二中间计算组合成Hessian矩阵计算。
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77.发明授权公开(公告)号：US09378164B2
公开(公告)日：2016-06-28
申请号：US13997651
申请日：2011-12-22
CPC分类号： G06F9/3016 , G06F9/327 , G06F9/3861 , G06F9/4806 , G06F9/4812 , G06F13/24
摘要： An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
摘要翻译： 描述了在半导体芯片上实现的指令流水线。 半导体芯片包括执行单元，以执行中断处理指令。 存储电路用于保存不同组的微操作，其中每组微操作都要处理不同的中断。 第一逻辑电路，用于执行一组所述微操作组，以处理所述集合设计的中断。 第二逻辑电路，用于在所述第一逻辑电路处理所述中断时将程序流返回到调用程序。
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公开(公告)号：US09360927B2
公开(公告)日：2016-06-07
申请号：US13992361
申请日：2011-09-06
申请人： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
发明人： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
摘要： In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于从加速器接收中断的方法，响应于该中断将恢复信号直接发送到小型核心，并向第一小型核心提供大型核心的执行状态的子集，以及 确定小型核心是否可以处理与该中断有关的请求，如果该确定是肯定的，则执行与该小核心中的该请求相对应的操作，否则将大的核心执行状态和恢复信号提供给该大核心 。 描述和要求保护其他实施例。
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公开(公告)号：US20140314323A1
公开(公告)日：2014-10-23
申请号：US14320092
申请日：2014-06-30
CPC分类号： G06K9/481 , G06K9/00973 , G06K9/4671 , G06K2009/485
摘要： Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
摘要翻译： 识别图像的方法和系统可以包括具有硬件模块的装置，该硬件模块具有对于图像中的多个向量的逻辑，基于图像矢量的偶数像素确定第一中间计算，并且基于奇数来确定第二中间计算 图像矢量的像素。 逻辑还可以将第一和第二中间计算组合成Hessian矩阵计算。
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公开(公告)号：US08858126B2
公开(公告)日：2014-10-14
申请号：US12567129
申请日：2009-09-25
申请人： Michael Glenn Morrison , Srikanth Bontha , Juan Seculi , Thomas Jerry Long, II , Jeremy Joseph Verellen , Ravishankar Iyer
发明人： Michael Glenn Morrison , Srikanth Bontha , Juan Seculi , Thomas Jerry Long, II , Jeremy Joseph Verellen , Ravishankar Iyer
CPC分类号： B23C5/1045 , B23C5/2221 , B23C2200/203 , B23C2200/361 , B23C2210/168 , Y10T407/1908 , Y10T407/192 , Y10T407/2272 , Y10T407/23
摘要： A cutting tool includes a body having a forward end and a rearward end. The forward end includes an insert-receiving pocket with a threaded hole having a center axis. The cutting tool further includes a cutting insert with a countersunk bore with a center axis. The cutting tool includes an error proofing feature for preventing the cutting insert to be properly mounted in an insert-receiving pocket when an offset distance between the center axis of the threaded hole of the insert-receiving pocket and the center axis of the countersunk bore of the cutting insert is greater than a predetermined percentage of the outer diameter of the threaded screw.
摘要翻译： 切割工具包括具有前端和后端的主体。 前端包括具有中心轴线的螺纹孔的插入物容纳袋。 切削工具还包括具有中心轴的埋头孔的切削刀片。 当刀片接收槽的螺纹孔的中心轴线与埋头孔的中心轴线之间的偏移距离为0°时，切削工具包括防止切削刀片适当地安装在刀片容纳槽中的防错特征 切削刀片大于螺纹螺杆的外径的预定百分比。
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