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340 条记录 (耗时 0.048 秒)

    Implantation of gate regions in semiconductor device fabrication
    75.
    发明授权
    Implantation of gate regions in semiconductor device fabrication 失效
    在半导体器件制造中植入栅极区域

    公开(公告)号：US07118997B2

    公开(公告)日：2006-10-10

    申请号：US10905977

    申请日：2005-01-28

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III.

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III.

    IPC分类号： H01L21/425

    CPC分类号： H01L29/66545 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659

    摘要： A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer essentially directly above the gate region essentially without removing the remainder of the resist layer; and (d) implanting the gate region essentially without implanting the semiconductor layer.

    摘要翻译： 一种注入栅极区域的方法，其基本上不注入将在其后形成源极/漏极区域的半导体层的区域。 该方法包括以下步骤：（i）在半导体层上提供（i）半导体层，（ii）栅极电介质层，（iii）栅极介电层上的栅极区域，其中栅极区域与 半导体层由栅介质层; （b）在栅介质层和栅极区上形成抗蚀剂层; （c）基本上直接在栅极区域上方去除抗蚀剂层的盖部分，而不去除抗蚀剂层的其余部分; 和（d）基本上不注入半导体层来注入栅极区域。

    Alternating phase mask built by additive film deposition
    77.
    发明授权
    Alternating phase mask built by additive film deposition 失效
    通过添加膜沉积建立的交替相位掩模

    公开(公告)号：US06998204B2

    公开(公告)日：2006-02-14

    申请号：US10707009

    申请日：2003-11-13

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

    IPC分类号： G01F9/00

    CPC分类号： G03F1/30 ,  G03F1/54 ,  G03F1/68

    摘要： The invention provides a method of forming a phase shift mask and the resulting phase shift mask. The method forms a non-transparent film on a transparent substrate and patterns an etch stop layer on the non-transparent film. The invention patterns the non-transparent film using the etch stop layer to expose areas of the transparent substrate. Next, the invention forms a mask on the non-transparent film to protect selected areas of the transparent substrate and forms a phase shift oxide on exposed areas of the transparent substrate. Subsequently, the mask is removed and the phase shift oxide is polished down to the etch stop layer, after which the etch stop layer is removed.

    摘要翻译： 本发明提供一种形成相移掩模的方法和所得到的相移掩模。 该方法在透明基板上形成不透明的薄膜，并在非透明薄膜上形成蚀刻停止层。 本发明使用蚀刻停止层来图案化非透明膜以暴露透明基底的区域。 接下来，本发明在非透明膜上形成掩模，以保护透明基板的选定区域，并在透明基板的曝光区域上形成相移氧化物。 随后，去除掩模并将相移氧化物抛光到蚀刻停止层，之后去除蚀刻停止层。

    Method for etching a semiconductor substrate using germanium hard mask
    78.
    发明授权
    Method for etching a semiconductor substrate using germanium hard mask 失效
    使用锗硬掩模蚀刻半导体衬底的方法

    公开(公告)号：US06867143B1

    公开(公告)日：2005-03-15

    申请号：US09599783

    申请日：2000-06-22

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

    IPC分类号： C23F4/00 ,  C23G1/00 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3213

    CPC分类号： H01L21/3081 ,  C23F4/00 ,  C23G1/00 ,  H01L21/3086 ,  H01L21/32134

    摘要： An etching process using germanium hard mask (25) includes forming a dielectric layer (15) over a major surface (11) of a semiconductor substrate (10) and depositing a metallic germanium layer (22) over the dielectric layer (15). The metallic germanium layer (22) is patterned through a photo resist (24) to form the germanium hard mask (25). The dielectric layer (15) is selectively etched through the germanium hard mask (25) to form a dielectric hard mask (35), through which the semiconductor substrate (10) is subsequently etched. After forming the dielectric hard mask (35), the germanium hard mask (25) is stripped away by oxidizing the metallic germanium hard mask (25) to transform it into a layer (27) of germanium oxide and rinsing the semiconductor substrate (10) in water to remove the germanium oxide layer (27). Preferably, the germanium hard mask (25) is removed before etching the semiconductor substrate (10).

    摘要翻译： 使用锗硬掩模（25）的蚀刻工艺包括在半导体衬底（10）的主表面（11）上形成电介质层（15），并在电介质层（15）上沉积金属锗层（22）。 通过光致抗蚀剂（24）将金属锗层（22）图案化以形成锗硬掩模（25）。 通过锗硬掩模（25）选择性地蚀刻电介质层（15）以形成电介质硬掩模（35），随后蚀刻半导体衬底（10）。 在形成电介质硬掩模（35）之后，通过氧化金属锗硬掩模（25）将锗硬掩模（25）剥离，将其转化成氧化锗层（27）并冲洗半导体衬底（10）， 在水中以除去氧化锗层（27）。 优选地，在蚀刻半导体衬底（10）之前去除锗硬掩模（25）。

    Borderless gate structures
    79.
    发明授权
    Borderless gate structures 有权
    无边界门结构

    公开(公告)号：US06531724B1

    公开(公告)日：2003-03-11

    申请号：US09686740

    申请日：2000-10-10

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

    IPC分类号： H01L29772

    CPC分类号： H01L21/76897 ,  H01L21/76888 ,  H01L21/76895

    摘要： A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.

    摘要翻译： 一种用于在晶体管中形成栅极导体帽的方法，包括以下步骤：a）形成多晶硅栅极导体; b）掺杂多晶硅栅极; c）掺杂扩散区域; 以及d）通过从选择性氮化物沉积和选择性表面氮化中选择的氮化方法来封盖栅极导体。 所得到的晶体管可以包括封盖栅极导体和无边界扩散接触，其中通过选择性氮化物沉积和选择性表面氮化中选择的氮化方法发生封盖，并且其中在氮化方法期间掩模一部分栅极导体以留下开口 接触区域用于局部互连或门接触。

    Structure for folded architecture pillar memory cell
    80.
    发明授权
    Structure for folded architecture pillar memory cell 有权
    折叠式立柱式记忆体结构

    公开(公告)号：US06440801B1

    公开(公告)日：2002-08-27

    申请号：US09604901

    申请日：2000-06-28

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

    IPC分类号： H01L21336

    CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

    摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

    摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。