公开(公告)号：US20130011980A1

公开(公告)日：2013-01-10

申请号：US13501711

申请日：2011-11-18

申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC分类号： H01L21/336 ,  B82Y40/00

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L29/775

摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

摘要翻译： 本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。 与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力 ，并减少泄漏电流和漏极引起的屏障降低（DIBL）。 另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

公开(公告)号：US20130001655A1

公开(公告)日：2013-01-03

申请号：US13582624

申请日：2011-08-17

申请人： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

发明人： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

IPC分类号： H01L23/38 ,  H01L29/80

CPC分类号： H01L23/38 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink.

摘要翻译： 本发明公开了一种具有肖特基源极/漏极的SOI场效应晶体管的散热结构，涉及微电子领域。 散热结构包括与漏极端子或者源极端子和漏极端子连接的两个孔，其分别填充有高热电系数的N型材料和具有高热电系数的P型材料。 在漏极端子附近，用于具有高热电系数的N型材料的金属线相对于漏极端子施加高电位，并且用于具有高热电系数的P型材料的金属线 漏极端子相对于漏极端子施加低电位。 在源极端子附近具有高热电系数的N型材料的金属线相对于源极端子施加高电位，并且在源极端子附近的用于P型材料的金属线是 相对于源极端子施加较低的电位。 通过珀耳帖效应，在本发明中，热量可以在热电材料和源极/漏极之间的接触部分处被吸收，并且同时在热电材料和底部电极金属之间的连接部分消散，因此 在器件的有源区域中产生的热量有效地传递到衬底并通过散热器散发。

公开(公告)号：US20120241712A1

公开(公告)日：2012-09-27

申请号：US13254570

申请日：2011-04-12

申请人： Yimao Cai ,  Ru Huang ,  Yangyuan Wang ,  Yinglong Huang

发明人： Yimao Cai ,  Ru Huang ,  Yangyuan Wang ,  Yinglong Huang

IPC分类号： H01L45/00 ,  H01L21/62

CPC分类号： H01L45/1233 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.

摘要翻译： 本发明公开了一种电阻式开关存储器及其制造方法。 电阻开关存储器包括插入在顶部和底部电极之间的衬底，顶部电极，底部电极和电阻开关材料，其中底部电极的中心部分向上突出以形成峰形，顶部 电极为板状。 底部电极的峰值结构降低了器件的功耗。 其制造方法包括通过腐蚀在基板的表面上形成峰值结构，然后在其上生长底部电极，以形成具有峰形的底部电极，以及沉积电阻式切换材料和顶部电极。 整个制造工艺简单，可以实现高集成度的装置。

公开(公告)号：US20120061637A1

公开(公告)日：2012-03-15

申请号：US13131601

申请日：2011-04-01

申请人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  LIjie Zhang ,  Yu Tang

发明人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  LIjie Zhang ,  Yu Tang

IPC分类号： H01L45/00

CPC分类号： H01L27/249 ,  H01L27/0688 ,  H01L27/101 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1691

摘要： The present invention relates to a field of nonvolatile memory technology in ULSI circuits manufacturing technology and discloses a 3D-structured resistive-switching memory array and a method for fabricating the same. The 3D-structured resistive-switching memory array according to the invention includes a substrate and a stack structure of bottom electrodes/isolation dielectric layers, deep trenches are etched in the stack structure of the bottom electrodes/the isolation dielectric layers; a resistive-switching material layer and a top electrode layer are deposited on sidewalls of the deep trenches, wherein the top electrodes and the bottom electrodes are crossed over each other on the sidewalls of the deep trenches with the resistive-switching material being interposed at cross-over points, each of the cross-over points forms one resistive-switching memory cell, and all of the resistive-switching memory cells form the 3D-structured resistive-switching memory array, and the 3D resistive-switching memory in the array are isolated by the isolation dielectric layers. According to the invention, the storage density of a resistive-switching memory can be improved, the process can be simplified, and the cost of the process can be reduced.

摘要翻译： 本发明涉及ULSI电路制造技术中的非易失性存储器技术领域，并公开了一种3D结构的电阻式开关存储器阵列及其制造方法。 根据本发明的3D结构的电阻式开关存储器阵列包括底部和底部电极/隔离电介质层的堆叠结构，在底部电极/隔离电介质层的堆叠结构中蚀刻深沟槽; 电阻切换材料层和顶部电极层沉积在深沟槽的侧壁上，其中顶部电极和底部电极在深沟槽的侧壁上彼此交叉，电阻切换材料插入在交叉 通过点，每个交叉点形成一个电阻式开关存储单元，并且所有的电阻式开关存储单元形成三维结构的电阻式开关存储器阵列，阵列中的3D电阻式切换存储器是 通过隔离绝缘层隔离。 根据本发明，能够提高电阻式切换存储器的存储密度，能够简化处理，能够降低处理成本。

公开(公告)号：US09099500B2

公开(公告)日：2015-08-04

申请号：US13503240

申请日：2011-11-18

申请人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

发明人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/02 ,  B82Y99/00

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/02603 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

摘要： The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

摘要翻译： 本发明公开了一种基于硅纳米线场效应晶体管的六边形可编程阵列及其制造方法。 阵列包括纳米线器件，纳米线器件连接区域和栅极连接区域，其中纳米线器件具有圆筒形状，并且包括硅纳米线通道，栅极介电层和栅极区域，纳米线通道被包围 通过所述栅极介电层，并且所述栅极介电层被所述栅极区域包围; 纳米线器件以六边形形式布置以形成编程单元，纳米线器件连接区域是三个纳米线器件的连接节点并且固定到硅支撑体。 本发明可以实现互连的复杂控制逻辑，并且适用于具有高集成度和高​​速度的数字/模拟和混合信号电路。

公开(公告)号：US09034702B2

公开(公告)日：2015-05-19

申请号：US13511123

申请日：2011-11-18

申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L29/42392 ,  H01L29/78696

摘要： Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.

摘要翻译： 本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。 该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。 该方法与传统的集成电路制造技术相兼容。 制造工艺简单方便，循环周期短。

公开(公告)号：US09018968B2

公开(公告)日：2015-04-28

申请号：US13879967

申请日：2012-02-28

申请人： Ru Huang ,  Jibin Zou ,  Changze Liu ,  Runsheng Wang ,  Jiewen Fan ,  Yangyuan Wang

发明人： Ru Huang ,  Jibin Zou ,  Changze Liu ,  Runsheng Wang ,  Jiewen Fan ,  Yangyuan Wang

IPC分类号： G01R31/02 ,  G01R31/26 ,  H01L21/66

CPC分类号： G01R31/2642 ,  G01R31/2621 ,  H01L22/14 ,  H01L22/34

摘要： Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices.

摘要翻译： 提出了一种用于测试半导体器件的栅介质层陷阱的密度和位置的方法。 测试方法使用由泄漏路径产生的栅极泄漏电流来测试具有小面积（有效沟道面积小于0.5平方微米）的半导体器件的栅极介电层中的阱密度和二维陷阱位置。 本发明特别适用于测试具有超小面积（有效通道面积小于0.05平方微米）的器件。 在不同材料和不同工艺的情况下，本方法可以获得栅极电介质层的陷阱分布情况。 在本方法中，器件要求简单，测试结构简单，测试成本低，测试快速，可在短时间内获得器件栅极电介质层的陷阱分布，适合 用于大批量的自动测试，特别适用于超小型半导体器件制造过程中的过程监控和成品质量检测。

公开(公告)号：US20140145139A1

公开(公告)日：2014-05-29

申请号：US13581470

申请日：2012-02-22

申请人： Ru Huang ,  Yu Tang ,  Yimao Cai ,  Lijie Zhang ,  Gengyu Yang ,  Shenghu Tan ,  Yue Pan ,  Poren Tang

发明人： Ru Huang ,  Yu Tang ,  Yimao Cai ,  Lijie Zhang ,  Gengyu Yang ,  Shenghu Tan ,  Yue Pan ,  Poren Tang

IPC分类号： H01L45/00

CPC分类号： H01L45/149 ,  H01L45/1675 ,  H01L51/0591

摘要： The present invention discloses a transparent flexible resistive memory and a fabrication method thereof. The transparent flexible resistive memory includes a transparent flexible substrate, a memory unit with a MIM capacitor structure over the substrate, wherein a bottom electrode and a top electrode of the memory unit are transparent and flexible, and an intermediate resistive layer is a transparent flexible film of poly(p-xylylene). Poly(p-xylylene) has excellent resistive characteristics. In the device, the substrate, the electrodes and the intermediate resistive layer are all formed of transparent flexible material so that a completely transparent flexible resistive memory which can be used in a transparent flexible electronic system is obtained.

摘要翻译： 本发明公开了一种透明柔性电阻式存储器及其制造方法。 透明柔性电阻存储器包括透明柔性衬底，在衬底上具有MIM电容器结构的存储单元，其中存储单元的底电极和顶电极是透明和柔性的，中间电阻层是透明柔性膜 的聚（对二甲苯）。 聚（对二甲苯）具有优异的电阻特性。 在该器件中，衬底，电极和中间电阻层均由透明柔性材料形成，从而获得可用于透明柔性电子系统中的完全透明的柔性电阻性存储器。

公开(公告)号：US08564031B2

公开(公告)日：2013-10-22

申请号：US13381633

申请日：2011-04-01

申请人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Gengyu Yang ,  Yujie Ai ,  Jiewen Fan

发明人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Gengyu Yang ,  Yujie Ai ,  Jiewen Fan

IPC分类号： H01L29/76

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775

摘要： The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).

摘要翻译： 本发明提供了一种耐高压横向双扩散晶体管。 横向双扩散MOS晶体管包括沟道区，栅极电介质，栅极区，源极区，漏极区，源极延伸区和漏极端S形漂移区，其中沟道区具有侧向 圆柱形硅纳米线结构，其上均匀地覆盖一层栅极电介质，栅极区在栅极电介质上，栅极区和栅极电介质完全围绕沟道区，源极延伸区位于源区和 漏极端S形漂移区域位于漏极区域和沟道区域之间，排水端S形漂移区域的平面图为单个或多个S形结构的形式，并且 相对介电常数为1-4的绝缘材料填充在S形结构内。

公开(公告)号：US20120313154A1

公开(公告)日：2012-12-13

申请号：US13501241

申请日：2011-10-14

申请人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Xin Huang ,  Yangyuan Wang

发明人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Xin Huang ,  Yangyuan Wang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7839

摘要： The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate. The combined-source structure according to the invention combines a Schottky barrier and a T-shaped gate, improves the performance of the device, and the fabrication method thereof is simple. Thus, a higher turn-on current, a lower leakage current, and a steeper subthreshold slope can be obtained, and the present application can be applied in the field of low power consumption and have a higher practical value.

摘要翻译： 本发明公开了一种具有低功耗的组合源结构的MOS晶体管，其涉及CMOS超大规模集成电路中的场效应晶体管逻辑器件和电路领域。 MOS晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，肖特基源区，高掺杂源极区和高掺杂漏极区。 控制栅极的一端延伸到高掺杂源极区域以形成T形，其中控制栅极的延伸区域是延伸栅极，控制栅极的其余区域是主栅极。 由延伸栅极覆盖的有源区是沟道区，其材料是衬底材料。 在肖特基源区域和延伸栅极下方的通道之间形成肖特基结。 根据本发明的组合源结构组合了肖特基势垒和T形门，提高了器件的性能，其制造方法简单。 因此，可以获得更高的导通电流，较低的漏电流和更陡的亚阈值斜率，并且本申请可以应用于低功耗领域并具有较高的实用价值。